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  1. #1
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    how to fix fanout and transition violations in DC

    Hi,

    In my dctcl file, the constraints for reset are as followings:

    set_drive 0 [find port rstb]
    set_dont_touch_network [find port rstb]
    set_resistance 0 [find net rstb]
    set_ideal_net [find net rstb]

    In vhdl file, a net connected to the reset of 256 registers is designed as:

    reg_clr <= '0' when new_iv='1' else rstb

    Since reset is set as don't touch, DC cannot optimize the reg_clr.

    I have set the max fanout to be 15 so there is the violation.

    There are also max_transition violations probably caused by high fanout network. It is shown as follows:

    max_transition

    Required Actual
    Net Transition Transition Slack
    -----------------------------------------------------------------
    reg_clr (dont_touch) 1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_0/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_1/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_2/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_3/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_4/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_5/data_reg_reg/RB
    1.50 8.91 -7.41 (VIOLATED)
    PIN : s2_6/data_reg_reg/RB


    Could anyone teach me how to optimize this type of network? It is conneted to reset via a combinational logic and I cannot use set_drive 0.

    Thanks.

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  2. #2
    Advanced Member level 4
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    Re: how to fix fanout and transition violations in DC

    Without floorplan, it is not relevant to fix DRV (trans/cap) during the synthesis step.
    This must be done during the PnR.


    1 members found this post helpful.

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