TrickyDicky
Advanced Member level 7
It synthesised to the logic that you describe. Things you do with variables can also be done with signals
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 -- use a variable to do the decode and then use that anywhere you need -- the decode compare, this is the only kind of situation where I use variables -- other than for modeling very large memories array (large variable arrays -- usually simulate faster, than an equivalent variable array) process (a, enable) variable decode : boolean; begin -- this is done in a blocking fashion, so the if statements are only considered after -- decode has been assigned either with a true or a false. decode := a = x"2400"; if (decode = true) then do_something <= do_true; else do_something <= do_false end if; -- now you can use it more than once if (decode = true and enable = '1') then some_enabled_logic <= do_enabled; end if end processs; -- done using a variable requires the variable assignment -- occurs outside the process to behave the same as the -- first example. signal decode : boolean; decode <= a = (x"2400"); process (a, enable) begin if (decode = true) then .... etc end process; -- use the compare directly without an intermediate variable do_something <= do_true when a = x"2400" else do_false;
Variables have no physical meaning in an FPGA...nor do signals. Both signals and variables are used as a method to describe functionality. A given signal or variable might end up being implemented as a specific identifiable thing in the final FPGA design...or it might not because it gets combined and optimized with other signals and variables that describe other logic. Use signals or variables, and simply understand how the language defines when they get updated. No need to try to attach physical meaning to any of it since the end result is look up tables, flip flops, memory and transistors driving fixed wiring.wats the meaning of variable physically in connection to a fpga ?
sorry, i couldnot follow, does that mean that we cant use variables while writing a synthesizing code. if no then its fine . but if we can write , then i want to know that how does it gets synthesized , wats the meaning of variable physically in connection to a fpga ?
As you basically don't think in terms of hardware and you are don't know VHDL very well...
NEVER USE VARIABLES EVER.