Sending data from PC to FPGA via Ethernet

beginner_EDA · Feb 10, 2015

Hello everybody,
I have implemented UDP offload example

**broken link removed**

in DE2-115 FPGA board.

FPGA to PC data transfer seems to be working which I observed via Wireshark.

but for reverse direction (PC to FPGA), I got stuck.

I want to test the reverse direction (PC to FPGA) by sending some test data from PC.

I would like to know:
For test purpose can Hyperterminal/Putty be used to send data from PC to FPGA via Ethernet Interface ? Do I need some additional setting?

OR
Is there any other alternative?

Regards

std_match · Feb 10, 2015

Try netcat (nc).

beginner_EDA · Feb 10, 2015

Hi,
thanks for the clue.
I am using windows 8 64 bit (not linux)

To send data from PC to FPGA using netcat(nc), first I created a file as:
C:\netcat-win32-1.11\netcat-1.11>echo 'udp text file' > udp_text_file.txt

and then try to send it as:
C:\netcat-win32-1.11\netcat-1.11>nc64 -uvv 10.0.0.1 49155 < udp_text_file.txt

but it shows following:
10.0.0.1: inverse host lookup failed: h_errno 11004: NO_DATA
(UNKNOWN) [10.0.0.1] 49155 (?): NETUNREACH
sent 0, rcvd 0: NOTSOCK

What's wrong here?

Regards

FvM · Feb 10, 2015

What do you see in wireshark? Does the FPGA side support address resolution protocol?

beginner_EDA · Feb 10, 2015

FvM said:
What do you see in wireshark? Does the FPGA side support address resolution protocol?

See attachment for wireshark.
I am just sending 1111...... from FPGA to PC for test purpose.

FvM · Feb 10, 2015

I would expect that the FPGA is sending to a host in the same subnet address range.

But I was actually asking about the Wireshark capture of PC to FPGA UDP packets, to see if you manage to send them at all.

mrflibble · Feb 10, 2015

beginner_EDA said:
but it shows following:
10.0.0.1: inverse host lookup failed: h_errno 11004: NO_DATA
(UNKNOWN) [10.0.0.1] 49155 (?): NETUNREACH
sent 0, rcvd 0: NOTSOCK

What's wrong here?

What's wrong there is your setup is just asking for trouble.

Couple of quick tips:
- use a dedicated network card for testing the fpga network stuff.
- connect the fpga and this dedicated network card using a direct cable. no hub/switch/router in between complicating things
- make sure you get a link. Assuming the PC side has gigabit capability the link negotiation should almost certainly go automagically. for 100 mbit you may need 1 cup of coffee.
- put the PC side and fpga on the same network, as in same address range.

So for example PC = 10.0.0.1/24 and fpga = 10.0.0.2/24 or whatever you like. But NOT curious combinations like the 10.0.0.1 and 169.254.208.251 as seen in your screenshot. That's just asking for routing related trouble.

Oh yeah, and start with small test packets first, say ~ 512 bytes. That avoids some other fun issues for your first tests.

beginner_EDA · Feb 11, 2015

FvM said:
I would expect that the FPGA is sending to a host in the same subnet address range.

But I was actually asking about the Wireshark capture of PC to FPGA UDP packets, to see if you manage to send them at all.

Hi, I set the same subnet address range in PC compared to FPGA.
and now netcat shows:
C:\netcat-win32-1.11\netcat-1.11>nc64 -uvv 10.0.0.1 6000 < udp_text_file.txt
10.0.0.1: inverse host lookup failed: h_errno 11004: NO_DATA
(UNKNOWN) [10.0.0.1] 6000 (?) open

I don't see any sending traffic (PC-> FPGA) in Wireshark.

on FPGA side, following configuration is set for IP, gateway and subnet:
IP4_ADDR(*ipaddr, 10, 0, 0, 1);
IP4_ADDR(*gw, 0, 0, 0, 0);
IP4_ADDR(*netmask, 255, 0, 0, 0);

What could be your suggestion?

beginner_EDA · Feb 11, 2015

mrflibble said:
Couple of quick tips: ............

Oh yeah, and start with small test packets first, say ~ 512 bytes. That avoids some other fun issues for your first tests.

Hi, I used the Tips you suggested and now netcat shows:
C:\netcat-win32-1.11\netcat-1.11>nc64 -uvv 10.0.0.1 6000 < udp_text_file.txt
10.0.0.1: inverse host lookup failed: h_errno 11004: NO_DATA
(UNKNOWN) [10.0.0.1] 6000 (?) open

As I am newbie in netcat, I didn't understand how to send ~ 512 bytes by command from netcat. could you please give me some hints.

and what could be your suggestion for the problem?

std_match · Feb 11, 2015

How is the IP address mapped to the FPGA MAC address?
I expect that the FPGA can't handle the arp protocol, so you should do a static mapping in the PC with the arp command.
It will work via switches as long as the PC and the FPGA are on the same subnet.

beginner_EDA · Feb 11, 2015

std_match said:
How is the IP address mapped to the FPGA MAC address?
I expect that the FPGA can't handle the arp protocol, so you should do a static mapping in the PC with the arp command.
It will work via switches as long as the PC and the FPGA are on the same subnet.

Hi,
I tried with static mapping in PC with arp command as:
arp -s ip_address mac_address
but I still have same error.

Alternatively I removed FPGA and just try to connect 2 PC (each windows 8 64 bit) together by LAN cable and tried to run UDP command of netcat as:
1st PC: C:\netcat-win32-1.11\netcat-1.11>nc64 -luvp 5000
2nd PC: C:\netcat-win32-1.11\netcat-1.11>nc64 -uvv 10.0.0.1 5000

It also have same error as with FPGA.

But with TCP command:
nc64 -lvp 5000
and
nc64 10.0.0.1 5000
Communication between both PC works fine.

I guess it has something to do with udp command or some additional setting of netcat.

Your concern about how IP address mapped to the FPGA MAC address i.e. function of ARP, its not implemented as far I understood. But FPGA -> PC data transfer is working.

Any suggestion please.

FvM · Feb 11, 2015

But FPGA -> PC data transfer is working

Is working means is received at the PC? This implies that the FPGA is not only sending the data with the correct IP address but also the right MAC address. If so, how did you retrieve the MAC address, by performing ARP or by putting in a known MAC address?

At the regular socket interface, the PC is expecting an IP address and trying to discover the corresponding MAC address for hosts in the local network by ARP protocol. If the host doesn't know ARP, it won't be reached.

beginner_EDA · Feb 11, 2015

FvM said:
Is working means is received at the PC? This implies that the FPGA is not only sending the data with the correct IP address but also the right MAC address. If so, how did you retrieve the MAC address, by performing ARP or by putting in a known MAC address?

Thanks for clearing the concept. Yes working means received at the PC (see attachment in above reply).
I am putting known MAC, IP and UDP port number of both source and destination in application c program as:

Code:

 UDP_PAYLOAD_INSERTER_WR_MAC_DST_HI  (UDP_INSERTER_0_BASE, 0xe0db55d6 );
    UDP_PAYLOAD_INSERTER_WR_MAC_DST_LO  (UDP_INSERTER_0_BASE,0x8f5f );
    UDP_PAYLOAD_INSERTER_WR_MAC_SRC_HI  (UDP_INSERTER_0_BASE, 0x0007edff);
    UDP_PAYLOAD_INSERTER_WR_MAC_SRC_LO  (UDP_INSERTER_0_BASE, 0x8f10);
    UDP_PAYLOAD_INSERTER_WR_IP_SRC      (UDP_INSERTER_0_BASE, 0x0a000001);
    UDP_PAYLOAD_INSERTER_WR_IP_DST      (UDP_INSERTER_0_BASE, 0xa9fed0fb);
    UDP_PAYLOAD_INSERTER_WR_UDP_PORTS   (UDP_INSERTER_0_BASE, 0xc002c003);

But I am not able to send data from PC to FPGA via netcat and getting error as mentioned in above reply.
Does it mean to send data from PC to FPGA, I also have to read(by setting base address) following registers corresponding to known MAC, IP and UDP port number of both source and destination in application c program:

Code:

#define UDP_PAYLOAD_INSERTER_RD_MAC_DST_HI(base)            IORD(base, 1)
#define UDP_PAYLOAD_INSERTER_RD_MAC_DST_LO(base)            IORD(base, 2)
#define UDP_PAYLOAD_INSERTER_RD_MAC_SRC_HI(base)            IORD(base, 3)
#define UDP_PAYLOAD_INSERTER_RD_MAC_SRC_LO(base)            IORD(base, 4)
#define UDP_PAYLOAD_INSERTER_RD_IP_SRC(base)                IORD(base, 5)
#define UDP_PAYLOAD_INSERTER_RD_IP_DST(base)                IORD(base, 6)
#define UDP_PAYLOAD_INSERTER_RD_UDP_PORTS(base)             IORD(base, 7)

?

mrflibble · Feb 11, 2015

The PC has to know the mac address of the FPGA if you want to send data from PC to FPGA. Just as the FPGA has to know the mac address of the PC when the FPGA is sending to PC.

When I'm too lazy to implement arp (which is quite often), then I use static arp on the sending side. Effectively you were using extremely static arp on the fpga side already. It only knows one mac. Anyways, on the PC you have to set up a static arp entry for the ip of the FPGA. That way when the PC wants to send something it can perform the ip to mac lookup.

Code:

arp -s 10.0.0.1 C0-FF-EE-C0-FF-EE

And replace the C0-FF-EE-C0-FF-EE with the mac of the fpga obviously.

beginner_EDA · Feb 12, 2015

mrflibble said:
Code:

arp -s 10.0.0.1 C0-FF-EE-C0-FF-EE

And replace the C0-FF-EE-C0-FF-EE with the mac of the fpga obviously.

Hi,
I did it but it has same error as before.
see screenshots in attachment.

is there anything to do with udp command in netcat? or there is something else?
I am asking because when I tried to run these netcat commands:

Code:

nc64 -luvp 6000
nc64 -uvv 10.0.0.1 6000

by connecting 2 computers (without FPGA), I also had similar error.
with TCP command:

Code:

nc64 -lvp 6000
nc64 10.0.0.1 6000

it works perfectly.

Regards

mrflibble · Feb 12, 2015

If you are reporting exactly what you did (and not just part of it), then I suspect I already have the "solution". But first let me ask you this:

Start wireshark capture, and then do your thing that "works perfectly".

Code:
with TCP command:
Code:

Code:

nc64 -lvp 6000 nc64 10.0.0.1 6000

it works perfectly.

Can you show a wireshark screenshot of the packets that produced?

...

Okay, I had a longer text but that would spoil it. Here's the md5 from part 2: c76d8d70f19243db0a1a3cec3d8e0ec6, just to check if I can see the future in Nine Inch Nails style. But let's see that wireshark screenshot for the above command.

beginner_EDA · Feb 12, 2015

mrflibble said:
If you are reporting exactly what you did (and not just part of it), then I suspect I already have the "solution". But first let me ask you this:

Start wireshark capture, and then do your thing that "works perfectly".

Hi,
please find the wireshark capture for both TCP and UDP and there corresponding commands I used in 2 different PCs.
in case of TCP, you see it works but for udp not.

- - - Updated - - -

Hi,
Thanks for the help. I found the solution.
First I have to reset everything by:
netsh interface ipv4 reset
restart computer then
netsh interface add neighbors "LAN connection name" "IP" "MAC" and then
arp -s "IP" "MAC" which basically same as before.
From sending PC even above mentioned error (like ...open) appears send data then on receiver side connection appears with warning and but one can still send/receive data as:
Warning: forward host lookup failed for PC1: h_errno 11001: HOST_NOT_F
OUND
connect to [10.0.0.1] from PC1 [10.0.0.10] 65233: HOST_NOT_FOUND
hello

I tried same with FPGA, it seems to work(as I observe sent data from PC to FPGA via wireshark).

Now I am confused from which port of FPGA I can receive this sent data from PC having only payload (and not also Header with payload).
I used this design:
**broken link removed**

From my understanding from Avalon streaming source of UDP Payload Extractor/ Avalon streaming sink of PRBS Packet checker.
Any suggestion please.

jamesmatt · Feb 12, 2015

Hello
I am doing the same job of sending the data from FPGA to PC. Can you please please let me know how you did please. I found that you did similar job.

Regards

mrflibble · Feb 13, 2015

beginner_EDA said:
Hi,
please find the wireshark capture for both TCP and UDP and there corresponding commands I used in 2 different PCs.
in case of TCP, you see it works but for udp not.

Thanks, that helps confirm certain suspicions. And it is as I suspected.

If I got all the moderately consistent bits together, then for the tcp case you were not sending any data either earlier on. For tcp you just noticed the SYN/ACK etc packets (at connection setup), and went "hey look, it is working". And then you tried the exact same thing with udp ... and hey, no packets, and so the udp case must not be working. The udp case was actually working just fine, but you didn't send any data and ... thus no packets.

If you open a socket, but then send no data, you will get what you were getting. UDP ==> no packets. TCP ==> SYN/ACK packets.
If you then actually send some data, you will see packets for both the tcp and the udp case. With tcp you will see more packets, because tcp has that whole message control thing.

And what's also amusing is that you don't complain about the receiving side for the PC-PC case. That gives the same message as the PC-FPGA case earlier on, but then on the source side.

Anyways, the moral of the story is: You do have to send data to actually see packets flowing for the udp case. For tcp you will see packets flowing even for the "no data sent" case, because packets are sent as soon as you open up a socket on the sending client side.

- - - Updated - - -

beginner_EDA said:
I tried same with FPGA, it seems to work(as I observe sent data from PC to FPGA via wireshark).

Now I am confused from which port of FPGA I can receive this sent data from PC having only payload (and not also Header with payload).

Not sure what you mean there? In either case you can extract the payload just fine. If you get full packet, then just skip a certain amount of bytes and start at the payload.

beginner_EDA · Feb 13, 2015

mrflibble said:
In either case you can extract the payload just fine. If you get full packet, then just skip a certain amount of bytes and start at the payload.

Thanks it helped.

I applied Signal Tap II logic analyzer directly at RX port of TSE working in RGMII mode:
ENET0_RX_DATA[0],
ENET0_RX_DATA[1],
ENET0_RX_DATA[2] and
ENET0_RX_DATA[3] with clock ENET0_RX_CLK.
and when I send data from Netcat(PC) to FPGA, I also see signal changes on these 4 bits pins of TSE in signal tap.
but received data in signal tap seems to be quite confusing and difficult to analyze.

The actual block diagram of the design is in attachment.
Avalon source/sink is 32 bit width.

From which port/pin should I receive sent data from PC(Netcat) to FPGA?
May be by exporting Avalon source/sink of one of the component.
Any idea please.

From my understanding Avalon streaming source(SRC) of TSE MAC will be fine for this purpose then I thought the packet coming from GEN (PRBS packet generator) component also passed through this. Then how to distinguish the packet is coming from GEN component or from PC (netcat)??

- - - Updated - - -

jamesmatt said:
Hello
I am doing the same job of sending the data from FPGA to PC. Can you please please let me know how you did please. I found that you did similar job.

Regards

Hi,
I just followed this tutorial:

**broken link removed**

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