i got an fatal error" Too many port connections. Expected 2, found 3"

i tried to compile a verilog code for divided by2 circuit using flip flop , its needs a feedback so i used a buffer at the output, the code got successful compilation but while loading i got this error



please anyone help me out , have any1 encountered these kind of errors

here is the code for divide by2 circuit

hi,

C:/altera/10.0/divdes.v(7): Too many port connections. Expected 2, found 3.

where is divdes.v?
are you sure you are compailing the right module....

regards

ramya15 said:

i tried to compile a verilog code for divided by2 circuit using flip flop , its needs a feedback so i used a buffer at the output, the code got successful compilation but while loading i got this error

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Code dot - [expand]
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# Loading work.my_buf
# ** Fatal: (vsim-3365) C:/altera/10.0/divdes.v(7): Too many port connections. Expected 2, found 3.
#    Time: 0 ns  Iteration: 0  Instance: /divi1/n1 File: C:/altera/10.0/buf.v
# FATAL ERROR while loading design
# Error loading design

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please anyone help me out , have any1 encountered these kind of errors

here is the code for divide by2 circuit

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Code Verilog - [expand]
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module divi1(q,qb,clk);
  output q,qb;
  input clk;
  wire x;
  wire y;
  wire a;
       my_nand n1(x,a,clk); // three ports, but my_nand only has two
     my_nand n2(y,x,clk);
     my_nand n3(q,x,qb);
     my_nand n4(qb,y,q);
     my_buf b1(a,qb);
     endmodule

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Click to expand...

You've likely defined the ports on my_nand incorrectly. As you did not post the code I can't say for sure, but the error indicates that the my_nand has only two ports and the instance on line 7 has three.

You should also make it a habit to name your files the same as the module name.

Re: i got an fatal error" Too many port connections. Expected 2, found 3"

yes, divides.v is the name of the compiled file
divi1 is the module name of compiled file divides.v

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when i simulated the nand gate without buffer code ,i got loaded.
after adding the buffer its not working out.
the coding for nand gate and inverter are correct.

Why didn't you post the my_buf code (and the my_nand code) I assuming that is somthing you wrote? You're wasting our time with multiple posts when someone experienced could just duplicate the problem and tell you what is wrong instead of trying to guess with information you supply (from someone without enough experience to even know what might be required information).

I'm going to guess it's due to using a file name that doesn't match the module name and you actually aare picking up an old (perviously compiled) working file. This is why I said it is a bad idea (actually very stupid) to name the file something other than the module name. Delete all the files in the simulation directory other than your RTL anf recompile.

Iteration: 0 Instance: /divi1/n1 File: C:/altera/10.0/buf.v

Click to expand...

It's very supicious that instance n1 seems to be pointing to an Altera buf.v file.