what is the problem with the FDCE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.fixed_pkg.all;


entity Fixed_point_lefting_scheme_5_3_fast_hdl is

GENERIC (n : INTEGER := 10);
Port ( clk : IN STD_LOGIC;
s_set : IN STD_LOGIC;
input_s : IN STD_LOGIC_VECTOR (n-1 downto 0);
even_output : OUT STD_LOGIC_VECTOR (n-1 downto 0);
odd_output : OUT STD_LOGIC_VECTOR (n-1 downto 0));

end Fixed_point_lefting_scheme_5_3_fast_hdl;

architecture Behavioral of Fixed_point_lefting_scheme_5_3_fast_hdl is

signal sel_ena : STD_LOGIC;

begin

stage_selction: PROCESS (clk, s_set)
begin

if (s_set = '0') then
sel_ena <= '0';
elsif (rising_edge(CLK)) then
sel_ena <= not (sel_ena);
end if;
end process stage_selction;


lifting_scheme: PROCESS (clk,s_set)

VARIABLE odd_o1 : ufixed (n-4 downto -3);
VARIABLE even_o1 : ufixed (n-4 downto -3);
VARIABLE odd_o2 : ufixed (n-4 downto -3);
VARIABLE even_o2 : ufixed (n-4 downto -3);
VARIABLE sum_eo1_eo2 : ufixed (n-4 downto -3);
VARIABLE odd_o3 : ufixed (n-4 downto -3);
VARIABLE even_o3 : ufixed (n-4 downto -3);
VARIABLE sum_oo2_oo3 : ufixed (n-4 downto -3);
VARIABLE temp_value : ufixed (n-3 downto -3);

BEGIN

if (s_set = '0') then
even_o1 := (others => '0');
odd_o1 := (others => '0');
even_o2 := (others => '0');
odd_o2 := (others => '0');
even_o3 := (others => '0');
odd_o3 := (others => '0');

elsif (rising_edge(CLK)) then
if (sel_ena = '0') then
even_o1 := to_ufixed(input_s, n-4, -3);
elsif (sel_ena = '1') then
odd_o1 := to_ufixed(input_s, n-4, -3);
end if;


case sel_ena is
when '0' =>
temp_value := (even_o1 + even_o2);
sum_eo1_eo2 := temp_value(n-4 downto -3);

-- multiply by alfa = 0.5
sum_eo1_eo2 := sum_eo1_eo2(n-4) & sum_eo1_eo2(n-4 downto -2);

temp_value := (odd_o1 - sum_eo1_eo2);
odd_o2 := temp_value(n-4 downto -3);
temp_value := (odd_o2 + odd_o3);
sum_oo2_oo3 := temp_value(n-4 downto -3);

-- multiply by beta = 0.25
sum_oo2_oo3 := sum_oo2_oo3(n-4) & sum_oo2_oo3(n-4) & sum_oo2_oo3(n-4 downto -1);

temp_value := even_o2 + sum_oo2_oo3;
even_o3 := temp_value(n-4 downto -3);
even_output <= to_slv (even_o3);
when others =>
even_o2 := (even_o1);
odd_o3 := odd_o2;
odd_output <= to_slv (odd_o3);
end case;

end if;

end process lifting_scheme;

end Behavioral;

Click to expand...

below is my code and it can be seen that i never use such number of flip flop

Click to expand...

FvM said:

I see quite a lot of FFs generated by your code. There are FFs for
1. Each signal bit that's assigned under control of rising_edge(clk)
2. Each variable bit that has to be kept between clock cycles like odd_o1, odd_o2, odd_o3, even_o1

Click to expand...

ads-ee said:

You have a lot of FDCE and FDE flipflops because you have enables in your code.

Code:

--anything using a templete like this:
Process(clk)
  If rising_edge(clk) then
    If some_signal = '0' then
      ...
    end if;
  end if;
End process;

Click to expand...