[SOLVED] Simulation Problems - Output signal displays false values in the beginning.

ads-ee said:

Nobody seems to have pointed out clearly why the output of the simulation shows the delay.

Code:

lut : process(clk,rst)
BEGIN
    if rst = '1' then
        address  <= "0000000000";
    elsif rising_edge(clk) then
        address  <= data_in;
    end if;
end process;

The address is the output of a clocked synchronous element (i.e. a register), therefore data_in is delayed by 1 clock cycle to produce address.

Code:

rom_lut : rom
port map (
    address  => address,
    clock    => clk,
    q        => data_out
);

The ROM uses a clock, therefore you will not see an output of the ROM for a given address until there is a clock and the address is stable prior to the rising clock edge.

Here is a diagram showing some data Do propagating through the code you wrote. There is a pipeline of registers that need to be filled before the corresponding DOo is generated.
View attachment 113216
You should note I've offset the transitions of data_in, address, and data_out from the clock edge to emphasize that the data is stable prior to and after the clock edge. You won't see this offset in your simulation unless you add unsynthesizable after # ns delays in your code (don't do this). You will instead see that the transitions line up with clock edges (in reality there are delta delays that actually offset the transitions from the clock edges)

Given that you think of your VHDL code as a program shows you don't have a full grasp on the fact that VHDL represents hardware and time in hardware is measured in clock cycles. You are thinking like a software programmer, where there really isn't much of a concept of pipelines that need to be filled and code executes in many clock cycles, but are interpreted as a single software "state".

Click to expand...