sreevenkjan
Full Member level 5
Hi all,
I have written a VHDL program to use ROM as look up table. The program compilation is done without any errors. However during simulation (screenshot is attached below) I get initialization problems where data_out values are read as 000 ans 3FF (hexadecimal values).
Since I have given data_in as random values and data_out values are correct after 2 clock cycles. Could you tell me why is it happening and where am I going wrong??
Thanks,
Sreeni
I have written a VHDL program to use ROM as look up table. The program compilation is done without any errors. However during simulation (screenshot is attached below) I get initialization problems where data_out values are read as 000 ans 3FF (hexadecimal values).
Since I have given data_in as random values and data_out values are correct after 2 clock cycles. Could you tell me why is it happening and where am I going wrong??
Thanks,
Sreeni