Ringkle
Newbie level 2
On Xilinx VC707 board, I choose a LVDS 200 MHz system clock provided by a fixed frequency oscillator, which connect to FPGA pins E19 and E18.
But there is no clock signal input to the FPGA, ie, there is no clock source when I implement my design.
How can I make this system clock work?
If anyone know please help. Example design or links may helpful.
https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf Page29
Thanks
Ringkle
But there is no clock signal input to the FPGA, ie, there is no clock source when I implement my design.
How can I make this system clock work?
If anyone know please help. Example design or links may helpful.
https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf Page29
Thanks
Ringkle