Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

asserting valid signals

Status
Not open for further replies.

anusha vasanta

Member level 1
Joined
Sep 23, 2014
Messages
34
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
251
Hi all,
is this a proper way of asserting and deasserting my valid signal.

Code:
  for (i=0;i< No_Patterns;i=i+1) begin      //apply inputs
  @ (posedge clk)
  #Clk2Q
  data_valid_in = 1;                       //assert valid signals
  cipherkey_valid_in = 1;
  plain_text = data_input_vectors[i];
  cipher_key = cipherkey_input_vectors[i];
  end
  
  @(posedge clk)
  data_valid_in = 0;                      //deassert valid signals
  cipherkey_valid_in = 0;
 

Yes. It is. The only thing you should remember while asserting valid signals is that these signals should be in sync with the data i.e. the valid should be asserted when the data is corrected and should be brought down otherwise.
 

thankyou. but here both are asserted and deasserted during posedge of clk how the actual process is gng on internally.
 

Simulate and observe the waveform and relate it to the code. You will then understand it then...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top