shaiko
Advanced Member level 5
Hello,
I'm sizing a VHDL input port with this line of code:
Y is a generic that's defined as:
Given this y, I expect x to be sized as: ( 3 downto 0 ).
However, modelsim 10.4 sizes it to ( 2 downto 0 ).
What's wrong here?
I'm sizing a VHDL input port with this line of code:
Code:
x: out unsigned ( positive ( floor ( log2 ( real ( y ) ) ) ) downto 0 ) ;
Code:
y : positive := 8 ;
However, modelsim 10.4 sizes it to ( 2 downto 0 ).
What's wrong here?