axi3795
Newbie level 2
Hi Everyone,
I wanna describe a RAM and ROM in VHDL and am not really getting what to do, so I will really appreciate if someone can help me.
Memory
8-Bit Addressable Memory, i.e. 8-bit wide Address Bus;
4-Bit Data-In-Bus;
4-Bit Data-Out-Bus;
One Program Memory Address Space implemented using an initialized ROM.
One Data Memory Address Space implemented using an uninitialized,
asynchronous RAM.
Asynchronous Write signal, MW = 1 to write, 0 to not write, i.e. re
Thank You,
I wanna describe a RAM and ROM in VHDL and am not really getting what to do, so I will really appreciate if someone can help me.
Memory
8-Bit Addressable Memory, i.e. 8-bit wide Address Bus;
4-Bit Data-In-Bus;
4-Bit Data-Out-Bus;
One Program Memory Address Space implemented using an initialized ROM.
One Data Memory Address Space implemented using an uninitialized,
asynchronous RAM.
Asynchronous Write signal, MW = 1 to write, 0 to not write, i.e. re
Thank You,