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How to extend 4-bit barrel shifter to 32-bit?

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delta136

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I'm having some trouble thinking of an algorithm for extending a 4-bit left shifter to 32-bits

Here's my 4 bit left shifter code:
Code: 
module left_barrel_shift_4(output [3:0] y,
                           input [3:0] b,
                           input [1:0] s);
  
	wire mux1_out, mux2_out, mux3_out, mux4_out;
  
  	mux_2x1 mux1(.y_out(mux1_out), .l0(b[0]), .l1(1'b0), .select(s[0]));
  	mux_2x1 mux2(.y_out(mux2_out), .l0(b[1]), .l1(b[0]), .select(s[0]));
  	mux_2x1 mux3(.y_out(mux3_out), .l0(b[1]), .l1(b[1]), .select(s[0]));
  	mux_2x1 mux4(.y_out(mux4_out), .l0(b[1]), .l1(b[2]), .select(s[0]));
  	
  	mux_2x1 mux5(.y_out(y[0]), .l0(mux1_out), .l1(1'b0), .select(s[1]));
  	mux_2x1 mux6(.y_out(y[1]), .l0(mux2_out), .l1(1'b0), .select(s[1]));
  	mux_2x1 mux7(.y_out(y[2]), .l0(mux3_out), .l1(mux1_out), .select(s[1]));
  	mux_2x1 mux8(.y_out(y[3]), .l0(mux4_out), .l1(mux2_out), .select(s[1]));
  
endmodule

I know I need to use a generate block, otherwise I'm going to be manually connecting 160 muxes. I'm having a lot of trouble figuring out the algorithm for the for-loop of the generate block though... any help or pointers would be greatly appreciated. This one has stumped me for a while now.

I know that zero needs to be plugged into each cascade of muxes, according to the index of 's'.
For example, the first cascade for s[0] = 2 ^ 0 = 1. Therefore there is one 0 coming into the mux.
The 5th cascade for s[4] = 2 ^ 4 = 16. Therefore there are sixteen 0's coming into the mux.

I also have to do a 32-bit right barrel shifter, so any help on that would be greatly appreciated as well!

Normally I would draw it out and figure out the algorithm, but I just can't picture 160 muxes :bang:
 

Thanks for the link, but I know how to use a generate block :)

The problem I'm having is the algorithm inside the for-loop for placing the 0's and output from previous cascaded muxes
 

Why are you doing this as instantiated 2 to 1 multiplexers?

It would be much simpler to do this as behavioral code.
Code Verilog - [expand]
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// 8-bit barrel shift
case (select)
  0 : bshft <=  d[7:0];
  1 : bshft <= {d[6:0], d[7]};   // change d[7] to 1'b0 if you want a left shift and not a barrel shift
  2 : bshft <= {d[5:0], d[7:6]}; // change d[7:6] to 2'b0...
  3 : bshft <= {d[4:0], d[7:5]}; // "
  4 : bshft <= {d[3:0], d[7:4]};
  5 : bshft <= {d[2:0], d[7:3]};
  6 : bshft <= {d[1:0], d[7:2]};
  7 : bshft <= {d[0], d[7:1]};
endcase;

Also you state you want a barrel shift but your code shows a plain left shift?
 
Last edited:

I have to do the barrel shifter at the gate-level as part of my assignment.

I'm only implementing the left barrel shifter for now, then I will implement the right barrel shifter after I can get the left one working first. Once both the left and right side are implemented, I can combine them into a real barrel shifter. Hopefully that explains it
 

delta136 said:
I have to do the barrel shifter at the gate-level as part of my assignment.

I'm only implementing the left barrel shifter for now, then I will implement the right barrel shifter after I can get the left one working first. Once both the left and right side are implemented, I can combine them into a real barrel shifter. Hopefully that explains it
Click to expand...

Good grief, what kind of idiotic assignment is that? Basically they are making you do something that nobody would do in industry. What next are you going to design a 64-bit out of order execution microprocessor using only 2-input NAND gates!? 8-O

If you want to use a generate and hook up all those muxes...you can use the generate genvar variable in an equation to select the correct inputs like 0 or another mux output. Use a spreadsheet or something to map out the selects and the input to outputs. At least that is what I would do to figure out the relationship of selects to mux inputs.

- - - Updated - - -

Truthfully I would probably "cheat" by creating the barrel shifter (which is different than a plain left shift) as behavioral code, then run it through a synthesis tool to generate a gate level netlist. I'd then hand the gate level netlist in. :evil:
 
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