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pipelining concept in rtl

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anusha vasanta

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Hi all,
do pipelining reduces the no.of clock cycles in rtl??
what do actually pipeline means in verilog is it implementing non-blocking statements or anything else??
thanx in advance
 

Hi Anusha,

Pipe lining is nothing but introducing registers in your data path. It does not reduce the clock cycles rather it will increase according to the no. of pipe lining added in the data path.
It is very useful when you want to optimize your design. Also it can be used to remove set up time violations.
 

Pipelining is usually done when the design is not able to meet the required operating frequency. Long combo paths are broken down into shorter paths by inserting registers in between. This reduces the combi delay and thus increases the operating frequency.
Registers are usually implemented in RTL by non blocking statements. But all non blocking statements do not infer registers.
 

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