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Help in running system verilog code given in SystemVerilog for Verification by Spear

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Shilpa-_-Singh

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Hello sir,
I am a newbie to system verilog and I was trying to run the following code given in spears book
Code: 
function void init(ref int f[5], input int start);
  foreach (f[i])
    f[i] = i + start;
endfunction
int fa[5];
initial begin
  init(fa, 5);
  foreach (fa[i])
    $display("fa[%0d] = %0d", i, fa[i]);
end

But due to some unfortunate reason it throws errors like "expecting class","unexpected initial"
Can someone please help me in making this code runnable in modelsim? and tell me what should be the output.


Thankyou :)
 

mrflibble said:
1) Put the entire code as posted inside a module.
2) Run it yourself. ;-)
Click to expand...



Sir I did as you said but it is still throwing an error " The task or function 'init' with ref arguments must be automatic."



the code that i used is
Code: 
module test();
function void init(ref int f[5], input int start);
  foreach (f[i])
    f[i] = i + start;
endfunction
int fa[5];
initial begin
  init(fa, 5);
  foreach (fa[i])
    $display("fa[%0d] = %0d", i, fa[i]);
end
endmodule


Kindly help!
 

How about I help you help yourself? ;-) Please read this short tutorial on systemverilog functions: https://www.asic-world.com/systemverilog/task_function2.html#Functions

And this one about passing by reference: https://www.asic-world.com/systemverilog/task_function5.html

Actually the error message is big hint on how to fix it...

- - - Updated - - -

Mmmh, I see that the link I gave you does not show that you should be declaring the function as automatic. Well, now you know, you should be declaring that function as automatic because you are passing an argument by reference.
 
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