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Bidirectional memory to non verilog

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forast

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I have a module for a bidirectional memory but I need to get it working with non-bidirectional lines. I'm thinking this is simple but I'm stuck. Here's the module

Code: 
module ram16x4(
	input [3:0] address,
	inout [3:0] data,
	input ce, we, oe
);

reg [0:15] [3:0] memory; //16 x 4 RAM
assign data = ~ce & we & ~oe ? memory[address] : 4'hz;

always@(*)
begin
if (ce == 0)
	if (we == 0 && oe == 1)
		memory[address] = data;
end
endmodule

Should i make the inout into something like:

Code: 
input [3:0] in
output [3:0] out
assign in = ~ce & ~we & oe ? memory[address] : 4'hz;
assign out = ~ce & we & ~oe ? memory[address] : 4'hz;

Please let me know if i'm on the right track and any help is appreciated.
 

You should have an 'address' input, 'in' input, 'out' output and 'ce','we' and 'oe' as inputs.
Why are you assigning to 'in'? 'in' is an input. You cannot assign to an input.
 
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    forast

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sharath666 said:
You should have an 'address' input, 'in' input, 'out' output and 'ce','we' and 'oe' as inputs.
Why are you assigning to 'in'? 'in' is an input. You cannot assign to an input.
Click to expand...

Since 'data' shared the inout, I thought I'd need the same in and outs to make it the same as the 'inout'? I'm not sure what to do or if I'm doing it correctly but that's what I got from it.
 

With this new RAM there are no bidirectional ports. This means that the the input & output data are on separate buses.
In this scenario you can only control the output buses(output from the RAM). The input bus is in input to you. You can only accept the data on this bus. You cannot control it.
 

forast said:
Since 'data' shared the inout, I thought I'd need the same in and outs to make it the same as the 'inout'? I'm not sure what to do or if I'm doing it correctly but that's what I got from it.
Click to expand...
This shows you aren't thinking in terms of hardware design. Think of hooking up ICs on a board. A inout port is a port that is a bidirectional port, it can either be an output (driving data out of the IC, which also drives the input) or it can be an input (output disabled Hi-Z) that is driven from an external source.

If you separate it out to have uni-directional ports you need an output port and an input port, The output port is driven by whatever drove the inout port in the first place i.e. the statement that has the inout port name on the LHS. The input port drives all the instances where the inout port was used on the RHS or in case/if/etc statements.

Regards
 

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