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Reducing delay from flop to logic in critical path

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pinkesh2001

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set_critical_range, synopsys

Hi all,

How do i reduce the delay from 1st flip flop to the logic. I am having a delay of 1.5n before reaching to a logic bcoz of which my slack is getting worst.

How do i optimize.
Buffering has made a delay worst as it a very datapath oriented block and with a high fanout with large cap.Its not a multicycle path.

Thanks in advance,

Pinkesh
 

Although the contents you mentioned are not very clear, several basic ways tackling such issue are listed:
(1) reduce the combinatory logic as short as possible
(2) use the DC optimization skills including the set_critical_range or set_max_delay commands
(3) in my opinion, you'd better modify your RTL codes which is more reusable and more valid for the synthesis if your clock frequency is not so large. For example it's less than 500Mhz. Often different coding methods can create different logic.
(4) use the latest verision of DC as possible which can partition the path to make the load reduced
 

Thanks Thomson,

But the think is according to the architecture the rtl pepole says that the path will be big as logic levels cannot be reduced.

I m using MAGMA as optimization tool.

The commands which u have given, I m not aware as I have not worked on Synopsys tools.

Is it possible to clone Flipflop so that i can reduce delay and also fanout.That flip flop output pin has fanout of 500.
Design working at 180MHz.

Thanks,

Pinkesh
 

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