pinkesh2001
Junior Member level 2
set_critical_range, synopsys
Hi all,
How do i reduce the delay from 1st flip flop to the logic. I am having a delay of 1.5n before reaching to a logic bcoz of which my slack is getting worst.
How do i optimize.
Buffering has made a delay worst as it a very datapath oriented block and with a high fanout with large cap.Its not a multicycle path.
Thanks in advance,
Pinkesh
Hi all,
How do i reduce the delay from 1st flip flop to the logic. I am having a delay of 1.5n before reaching to a logic bcoz of which my slack is getting worst.
How do i optimize.
Buffering has made a delay worst as it a very datapath oriented block and with a high fanout with large cap.Its not a multicycle path.
Thanks in advance,
Pinkesh