# Power Analysis Tools

1. ## Power Analysis Tools

Hi All,

What are the most popular tools for Power Analysis? How can they help to reduce power consumption (static+dynamic)?

Thank you!

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3. ## Re: Power Analysis Tools

I am not sure how useful primetime is...

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4. ## Re: Power Analysis Tools

As for me, it's hard to understand how Power Analysis might be done without functional vectors... How should the tool understand the design behavioral? As for Gate Level Power Analysis, functional vectors are also required. Correct?

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Besides the automatic gated clock insertions, what another low power techniques might be implemented in RTL?

5. ## Re: Power Analysis Tools

Originally Posted by sharath666
I am not sure how useful primetime is...
There's PrimeTime PX, which has power analysis.

Design Compiler and RTL Compiler are commonly used for post-synthesis power analysis.

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Originally Posted by ivlsi
As for me, it's hard to understand how Power Analysis might be done without functional vectors...
You need functional vectors for sensible analysis. i.e. with most tools you will need to generate and read in a VCD file.
Originally Posted by ivlsi
Besides the automatic gated clock insertions, what another low power techniques might be implemented in RTL?
Operand gating (where you add logic at the start of a logic cone to prevent toggling in unused circuits).
Adding clock gating manually, which can gate the clock more efficiently than automatic clock gating.

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6. ## Re: Power Analysis Tools

The question depends on what are you trying to get out of power analysis
a) Chip power reduction: If you come up with a new circuit( clock gater or clock buffer). You can estimate the power reduction from one design to another using Prime Power. Prime Power is an analysis tool, it is highly depended on the power modeling inside the .libs that you use. most of the timing you will find power is not very cleanly modeled in the .libs.
b) IR/EM drop: Here the RTL is activated using worst case vector( scan mode and scan_in=0101010...stream so maximum toggling). Using the VCD file, the entire design is activate using Redhawk cell models and current is calculated drawn from the VDD. This is worst case analysis to find out hot spots in the design.
c) XA(synopsys tool) : This is used for doing spice level power analysis on individual blocks to avoid IR drop.

Most of the timing tools ( Tempus from Cadence) are capable of doing power recovery keeping timing in mind. But usually it is after the timing is done. The synthesis tool has the goal to reduce the area of the chip which in effect reduces the dynamic power. Less area->less cap -> less dynamic power.

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