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[SOLVED] system verilog input randamization problem

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dipin

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hi,

i am verifying a design using system verilog test bench.
input to the design are being randamized. my input is 16 bit width.

in_data <= $urandom_range(1000,9000);

in this ,is there any way to know how much %(percentage) of input is given to the design ???
in between 1000 and 9000 how many inputs are given to the design
( in %) . if anybody know please help


thanks & regards
 

$urandom_range gives you a uniform random distribution (flat). In your case there will be 1/9000% in each "bin".
 

Hi ,

For a testbench in system verilog , if we randomize the input , say 16 bit width ,it will have 65536

test cases right. how we will know all the cases are covered or not ?????

is it possible to know how much % of these test cases are covered
thanks & regards
 

Define a covergroup and add a coverpoint for in_data. Run simulation, and then you can check the coverage % in the gui of your favorite simulator.
 
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hi ,
thanku mrfibble.

Code: 
class transaction;
  
  randc bit [15:0] indata;
  
  endclass
  
  covergroup covindata;
  
  tr_in_data : coverpoint tr.indata
  
  {
   bins ZERO={0};
   bins SMALLER ={[1:16368]};
   bins MEDIUM ={[16368:32768]};
   bins LARGE ={[32769:65534]};
   bins MAX = {65535};
  }
  
  endgroup
  
  
  transaction tr = new;
  covindata ck = new;



..
always@(posedgeclk) begin
....
 
  ck.sample(); 
  ..
end

this is the code i have written. but in this for ai nput of 24700, it is showing 100 % coverage(24700 is the number of input ...i think atlest for a 65535 it must show 100% . so i think there is some problem with my code)

(coverage means group coverage)
did anybody know why??

actually iam using modelsim. is there any problem with my code??
if any problemis thre please let me know.

thanks & regards
 
Last edited:

Could be your code. Could also be your assumptions. The reason I mention the assumptions is because you say "think atlest for a 65535 it must show 100%". Why do you think a single input value of 65535 has anything to do with 100% coverage? Just because 65535 is the maximum value of the signal you are looking at doesn't make coverage 100%.

Just to check what you mean (because I have no idea) ... do you associate a value of indata=32768 with 50% coverage? And indata=0 with 0% coverage? Please don't shoot me for asking this potentially silly question, but I've learned it is better not to make any assumptions. :)
 

hi
mrflibble said:
Could be your code. Could also be your assumptions. The reason I mention the assumptions is because you say "think atlest for a 65535 it must show 100%". Why do you think a single input value of 65535 has anything to do with 100% coverage? Just because 65535 is the maximum value of the signal you are looking at doesn't make coverage 100%.

Just to check what you mean (because I have no idea) ... do you associate a value of indata=32768 with 50% coverage? And indata=0 with 0% coverage? Please don't shoot me for asking this potentially silly question, but I've learned it is better not to make any assumptions. :)
Click to expand...

in the above code, i am checking input coverage . input widrth is 16 bit ,so there will be 65535 inputs . so 100% coverage means all the input must be covered right?? . but for me when the number of input comes to 24700 its showing 100% coverage.....this is my problem..before taking all the inputs ,its showing 100% coverage.
thanks
 

Code: 
{
   bins ZERO={0};
   bins SMALLER ={[1:16368]};
   bins MEDIUM ={[16368:32768]};
   bins LARGE ={[32769:65534]};
   bins MAX = {65535};
  }

That's 5 bins. You can get a 100% coverage with just 5 lucky numbers. Suppose I generate 5 random numbers, and they happen to be 0, 1, 16368, 32769 and 65535, then all the bins have been hit at least once. And thus 100% coverage.

So your code it just fine IMO. Now slightly tweak your assumptions and you're good to go. ;-)

- - - Updated - - -

In fact, you can hit all the bins with just 4 numbers I noticed. 0, 16368, 32769 and 65535 and tadaaa 100% coverage. You have some overlap (16368) between the SMALLER and MEDIUM bins.
 
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hi ,

thank you mrfibble:thumbsup:

regards
 

There is no way to do this using a covergroup without creating 8000 bins. You could write:

Code: 
covergroup covindata;
  
  tr_in_data : coverpoint tr.indata
  
  {
   bins ALL[8000]={1000:9000};
  }
  
  endgroup

But you have to ask yourself "is this a productive use of simulation CPU cycles?" Using ALL[64] would give you 64 evenly distributed bins and a good statistical representation of coverage. The purpose of binning as in the example (SMALL, MEDIUM, LARGE) is to provide interesting corner cases that need to be covered without being exhaustive. But one needs to know the design requirements to know how to specify that.

If you are just curious and want to report how many unique numbers were generated, you could declare an array of bits, and set a bit for each value generated, then sum this bits at the end.
 
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