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    A question on first order ΔΣ modulator

    Dear all,

    I am trying to design a single-bit first order delta-sigma ADC. The architecture that I am using is the very simple single ended ΔΣ modulator. The modulator is supposed to work for audio band signals (20-20KHz). The clock signal that is used is a 2.56MHz pulse. Therefore OSR is 64.
    Switches that i used are the simple Tgate switches, a simple single stage amplifier is used for the sc-integrator. Also a simple two stage amplifier is used for the 1-bit ADC. The 1-bit DAC is realized with a simple inverter. The positive voltage of the DAC is +VREF and the negative voltage is -VREF. Capacitor sizes are equal to 1pF.

    Full schematic of the modulator and the simulation results are shown in this link:

    https://www.dropbox.com/s/k1tn764g58agk28/ADC.pdf?dl=0

    1- What is the relation between the (+VREF) and (-VREF) of the DAC in the feedback loop with respect to the input signal amplitude, and supply voltage? Should the difference between (+VREF) and (-VREF) be more ( or less) than input peak to peak voltage?

    2- Is there any rule of thumb that you can use to make sure that your modulator is working? How can I find out that my modulator is/isn't working?

    3- The average of the digital output signal of the 1-bit ADC should follow the average input signal. However, as it is clear in my simulation results, when the input signal reaches its positive (negative) peak, the output digital signal is logic low (high). This shows that my modulator output is the inverse of the input signal. I don't know what may cause this?

    I will greatly appreciate it if you would kindly guide me. Thanks,
    Last edited by FvM; 25th November 2014 at 08:14. Reason: Downnloaded external file to Edaboard

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