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  1. #1
    Member level 1
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    How to simulate a VHDL/Verilog code in Cadence Virtuoso ADE?

    Hi,
    First time I am trying to compile and simulate a simple VHDL file in Virutoso ADE.
    Initially I created a symbol and then updated VHDL file, compiled and generated the entity, behav of the vdhl file. Then added this symbol in a testbench, applied analog sources (VDC- 0 or 1) as inputs to the module. The simulator does not run this code.

    As I studied the config required. Are files like cds.lib , hdl.var, setup.loc ..etc required in the ADE spectre simulator. Could you tell me the procedure for this, I dont want use NC-VHDL simulator.

    Thank you,,

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  2. #2
    Junior Member level 2
    Points: 500, Level: 4

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    Re: How to simulate a VHDL/Verilog code in Cadence Virtuoso ADE?

    Maybe you can import VHDL/verilog netlist (synthesized by DC or other tools) directly into virtuoso environment. Then a new schematic will be generated and can be used to do further simulation in ADE.

    Regards,



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