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FinFET simulation in 16nm in HSPICE

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electronics20

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Dear everyone
I need to simulate an SRAM cell in HSPICE via FinFET technology. How do I perform this? It means, for example, in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this instruction?
Many Thanks
 

electronics20 said:
... in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this construction?
Click to expand...

Actually the same, at least for a single gate FinFET (incl. Intel's Tri-gate device). Just the physical structure is (very) different.
 
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