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How to make my VHDL core protected or make an IP-Core?

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nashafi

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Hi,

I have designed a MAP deocder architecture flow here at my research group. I am now exploring the option of giving it for commercial use. But i have no clue as how i can protect my VHDL code and still give some one some thign which they can use to target any FPGA platform or may be change and timing requirements etc.
I was thinking may be .edf file is an option. but is it secure or there is a way to get VHDL back from edf.
I would appreciate a discussuin on this issue. As it will help all new designers.

Thanks,

-Nauman
 

I guess most HDL simulators have an options for the users to encript their HDL sources. You may look up the user manu of the HDL simulator you are using.

I remember that Synopsis's VCS has such an option for users.

Good luck!

Regareds,
rprince006,
 

Hi

For sysnthesys
EDIF is good there is no means known to get back to VHDL
If you are using Altera FPGA you can export a VQM ( Verilog netlist file ) file
wich is usable but cannot be edited . Xilinx should have a similar netlist format
( XNF I think )

Regards
 

Hi

Another good solution is to deliver your IP-core only as hard IP semy-custom VLSI block. In this case it is very difficult to reuse core without you.

If you want to keep your IP do not offer any VHDL syntesizable source to anyone. Only deliver your IP in some implementation ready format.

If you use RTL formats it is easy to migrate your IP-core to different technologies. So I think that only technology dependant delivery option is secure solution.

Regards
 

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