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for exam, following process has latch inference.
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process(a, sel)
begin
if sel = '1' then
y <= a;
end if; -- no else statement refers latch!
end process;
==================
if you want to design combinational ckt, then you must describe all cases of inputs.
In VHDL, not describing case is treated as hold state, hence synthesizing results a latch to store the state.
VHDL is derived from ADA which is very strict language without any space for
uncertainty.
So if you do not specify some condition for signal synthesizer assumes last signal state not some default value.
Boole equation for simple D-Latch is:
Q=(D & LE) | (Q & D) | (Q & !LE)
Q(LE==0)=Q & D | Q=Q
Q(LE==1)=D | Q & D=D
When LE signal is going from 1 to 0 D-latch keeps last state of Q.
If you keep last value of signal Q for some combinations of input signals you have parasite (unwanted) latch intstead combinational logic without feedback loops.
If you do not instantiate a latch from tool technology library, you need to code it for the tool to sense you intend latch storage. In many cases you would simply want to infer latch rather than using it directly from the supported device library because you would remain technology independent.
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