[SOLVED] CMOS Challenge #2: Help fix this register

Hi again dear forum members,

Here's another CMOS challenge that I wanted to share with you. I have been fighting for a while with reverse engineering this cell register (presumed register) and haven't managed to get it to work correctly under irsim, if my understanding is correct this should be a flip flop type register, but I could be wrong, although having successfully recreated a couple of other registers i'm pretty sure this should be one too.

Below are three slides with information:

#1 contains a couple of photos with full M1/M2 metal and no metal, unfortunately I don't have a shot that will show the m1 interconnect alone... The left most element is a clock inverter.

#2 My own implementation of this cell in Magic. You can also download the magic and irsim files from here.

#3 The IRSIM output. As you will see the output does not make sense if this was a working flipflop.

Thanks for your help! ;-)

Output looks normal me ... for "a" gated input & clock gated output for an RZ signal.

Hi papanatas

I see output ok at pattern "01" but after that something look funny to me

@SunnySkyguy thanks for the feedback, that actually helped me looking at it with different eyes. It happens that this design requires a certain initialization: "data" and "a" need to be low when the clock begins, then "a" needs to go high in order for it to work.

After doing so the register works ok.

Thanks all for your feedback, case closed.