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Doubt in Modelsim, simulation taking more time, I am doing correctly?

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abu9022

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Hi Friends,

when I am running vsim tb_func32 -do "run -all" in modelsim, running for 30 minutes still didnt get final output

I dont know much about modelsim, I have doubt what I am doing is correct or something wrong?

Code: 
vsim tb_func32 -do "run -all"
# vsim -do {run -all} tb_func32 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.target
# Loading ieee.std_logic_arith(body)
# Loading work.device
# Loading std.textio(body)
# Loading work.config
# Loading work.mmuconfig
# Loading work.sparcv8
# Loading work.iface
# Loading work.tblib
# Loading work.leonlib
# Loading ieee.std_logic_unsigned(body)
# Loading work.debug(body)
# Loading work.tb_func32
# Loading work.tbleon(behav)
# Loading work.tbgen(behav)
# Loading work.tech_map
# Loading work.leon(rtl)
# Loading work.amba
# Loading work.ambacomp
# Loading work.mcore(rtl)
# Loading work.rstgen(rtl)
# Loading work.ahbarb(rtl)
# Loading work.apbmst(rtl)
# Loading work.fpulib
# Loading work.proc(rtl)
# Loading work.macro(body)
# Loading work.multlib
# Loading work.iu(synth)
# Loading work.iu_verilog1
# Loading work.iu_syn_updated
# Loading work.AND2_X1
# Loading work.OR2_X1
# Loading work.OR4_X1
# Loading work.OR3_X1
# Loading work.OAI33_X1
# Loading work.NOR2_X1
# Loading work.INV_X1
# Loading work.DLH_X1
# Loading work.XOR2_X1
# Loading work.NAND2_X1
# Loading work.AOI22_X1
# Loading work.AOI21_X1
# Loading work.NOR3_X2
# Loading work.NOR2_X2
# Loading work.INV_X4
# Loading work.NAND2_X2
# Loading work.AND3_X4
# Loading work.AND2_X4
# Loading work.NOR2_X4
# Loading work.OR2_X4
# Loading work.BUF_X4
# Loading work.INV_X16
# Loading work.OAI22_X2
# Loading work.OAI211_X4
# Loading work.MUX2_X2
# Loading work.DLH_X2
# Loading work.INV_X8
# Loading work.AND4_X4
# Loading work.NAND2_X4
# Loading work.OR3_X4
# Loading work.XNOR2_X2
# Loading work.OAI211_X2
# Loading work.MUX2_X1
# Loading work.OAI221_X2
# Loading work.OAI21_X1
# Loading work.AND3_X2
# Loading work.OAI21_X2
# Loading work.NAND3_X1
# Loading work.OAI211_X1
# Loading work.OAI22_X1
# Loading work.NOR3_X1
# Loading work.OAI222_X1
# Loading work.INV_X2
# Loading work.NOR4_X1
# Loading work.AND2_X2
# Loading work.AOI211_X1
# Loading work.NAND4_X1
# Loading work.OR2_X2
# Loading work.AOI22_X2
# Loading work.AOI21_X2
# Loading work.NAND3_X2
# Loading work.AOI211_X2
# Loading work.AOI221_X2
# Loading work.NOR4_X2
# Loading work.OAI222_X2
# Loading work.AOI222_X1
# Loading work.AND4_X2
# Loading work.AOI221_X1
# Loading work.XNOR2_X1
# Loading work.NAND4_X2
# Loading work.iu_DW01_inc_1
# Loading work.XOR2_X2
# Loading work.iu_DW01_add_5
# Loading work.iu_DW01_add_4
# Loading work.iu_DW01_add_3
# Loading work.NOR3_X4
# Loading work.NAND3_X4
# Loading work.OAI21_X4
# Loading work.AOI21_X4
# Loading work.iu_DW01_sub_1
# Loading work.iu_DW01_cmp6_5
# Loading work.iu_DW01_cmp6_4
# Loading work.iu_DW01_cmp6_3
# Loading work.iu_DW01_cmp6_2
# Loading work.iu_DW01_cmp6_1
# Loading work.iu_DW01_cmp6_0
# ** Warning: (vsim-PLI-3003) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(37): [TOFD] - System task or function '$set_gate_level_monitoring' is not defined.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
# ** Warning: (vsim-PLI-3003) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(38): [TOFD] - System task or function '$set_toggle_region' is not defined.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
# ** Warning: (vsim-PLI-3003) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(39): [TOFD] - System task or function '$toggle_start' is not defined.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
# ** Warning: (vsim-PLI-3003) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(44): [TOFD] - System task or function '$toggle_stop' is not defined.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
# ** Warning: (vsim-PLI-3003) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(45): [TOFD] - System task or function '$toggle_report' is not defined.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
# Loading work.tech_atc18
# Loading work.tech_atc25
# Loading work.tech_atc35
# Loading work.tech_fs90
# Loading work.tech_umc18
# Loading work.tech_generic
# Loading work.tech_virtex
# Loading work.tech_virtex2
# Loading work.tech_tsmc25
# Loading work.tech_proasic
# Loading work.tech_axcel
# Loading work.regfile_iu(rtl)
# Loading work.virtex2_regfile(behav)
# Loading work.virtex2_complib
# Loading work.virtex2_dpram(behav)
# Loading work.ramb16_s36_s36(behav)
# Loading work.ram16_sx_sx(behav)
# Loading work.cache(rtl)
# Loading work.icache(rtl)
# Loading work.dcache(rtl)
# Loading work.acache(rtl)
# Loading work.cachemem(rtl)
# Loading work.syncram(behav)
# Loading work.virtex2_syncram(behav)
# Loading work.ramb16_s36(behav)
# Loading work.generic_syncram(behavioral)
# Loading work.dpsyncram(behav)
# Loading work.ramb16_s9(behav)
# Loading work.dsu(rtl)
# Loading work.dsu_mem(rtl)
# Loading work.dcom(struct)
# Loading work.ahbmst(rtl)
# Loading work.dcom_uart(rtl)
# Loading work.mctrl(rtl)
# Loading work.lconf(rtl)
# Loading work.timers(rtl)
# Loading work.uart(rtl)
# Loading work.irqctrl(rtl)
# Loading ieee.std_logic_signed(body)
# Loading work.ioport(rtl)
# Loading work.clkgen(rtl)
# Loading work.generic_clkgen(rtl)
# Loading work.smpad(rtl)
# Loading work.gensmpad(rtl)
# Loading work.inpad(rtl)
# Loading work.geninpad(rtl)
# Loading work.outpad(rtl)
# Loading work.genoutpad(rtl)
# Loading work.iopad(rtl)
# Loading work.geniopad(rtl)
# Loading work.smiopad(rtl)
# Loading work.iram(behavioral)
# Loading work.testmod(behav)
# Loading work.seq1
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11351): [TFMPC] - Too few port connections. Expected 5, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/add_554
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11351): [TFMPC] - Missing connection for port 'CO'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11372): [TFMPC] - Too few port connections. Expected 5, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/add_1612
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11372): [TFMPC] - Missing connection for port 'CO'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11384): [TFMPC] - Too few port connections. Expected 5, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/add_1_root_add_1594_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11384): [TFMPC] - Missing connection for port 'CO'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11396): [TFMPC] - Too few port connections. Expected 5, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/sub_1_root_sub_1593_S2_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11396): [TFMPC] - Missing connection for port 'CO'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/eq_1079_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11401): [TFMPC] - Missing connection for port 'NE'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/eq_1076_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11406): [TFMPC] - Missing connection for port 'NE'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/eq_1061_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11409): [TFMPC] - Missing connection for port 'NE'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/eq_1058_2
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11412): [TFMPC] - Missing connection for port 'NE'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/r820
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11416): [TFMPC] - Missing connection for port 'NE'.
# ** Warning: (vsim-3017) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Too few port connections. Expected 9, found 4.
#         Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1/iu2/r819
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Missing connection for port 'LT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Missing connection for port 'GT'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Missing connection for port 'LE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Missing connection for port 'GE'.
# ** Warning: (vsim-3722) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_syn_updated.v(11419): [TFMPC] - Missing connection for port 'NE'.
# run -all 
# LEON-2 generic testbench (leon2-1.0.30-xst)
# Bug reports to Jiri Gaisler, jiri@gaisler.com
# 
# Testbench configuration:
# 32 kbyte 32-bit rom, 0-ws
# 2x128 kbyte 32-bit ram, 2x64 Mbyte SDRAM
#

time (is increasing): 222, 331, 830 ns (current time) Delta:2 sim :/tbleon
 

mrflibble said:
Evaluation versions of modelsim are slowed down considerably if they go beyond a certain amount of code. Don't know the exact details. You'd have to look it up on the Mentor website.

For example see: https://www.mentor.com/company/higher_ed/modelsim-student-edition
Click to expand...

I am running Integer Unit in LEON2 Processor, code(design file) also very long(13886 lines) and having testbench

So, I want to wait until simulation finishes?

Current Time 617, 509, 720 ns
 

13000+ lines will take many hours to run. If all your code is in Verilog you can try using Icarus Verilog.
 
ads-ee said:
13000+ lines will take many hours to run. If all your code is in Verilog you can try using Icarus Verilog.
Click to expand...

Given the library imports, it looks like VHDL.

To the OP: what version of modesim is it? What testbench is this? is it a self checking one?

Testbenches can take a long time to run depending on the situation and the code. Try putting a xilinx MIG or GTX model in your code - make sure you have a bed ready for the sleeping you'll need between sim runs...
 
TrickyDicky said:
Given the library imports, it looks like VHDL.

To the OP: what version of modesim is it? What testbench is this? is it a self checking one?

Testbenches can take a long time to run depending on the situation and the code. Try putting a xilinx MIG or GTX model in your code - make sure you have a bed ready for the sleeping you'll need between sim runs...
Click to expand...


Hi Friends

Actually my design in verilog gate level netlist, rest of the test benches are in vhdl
I am using QuestaSim 6.4c

Current Time:2, 677, 082, 510 ns
 

Since you're using mixed vhdl/verilog I think icarus is right out. Anyways, if you are going to be running several simulated seconds of a large design then yes, that is going to take a while. Multiple hours is not unusual. Or days, since days is just multiple hours repeated a few times. ;)

And AFAIK Questa has no evaluation version with reduced speed, so presumably you are already running at the maximum speed. Sounds like you'll just have to be patient, or adopt another test strategy.

- - - Updated - - -

@abu9022: Question out of interest, do you happen to be from India? Some hints in the use of language is why I ask.
 

mrflibble said:
Since you're using mixed vhdl/verilog I think icarus is right out. Anyways, if you are going to be running several simulated seconds of a large design then yes, that is going to take a while. Multiple hours is not unusual. Or days, since days is just multiple hours repeated a few times. ;)

And AFAIK Questa has no evaluation version with reduced speed, so presumably you are already running at the maximum speed. Sounds like you'll just have to be patient, or adopt another test strategy.

- - - Updated - - -

@abu9022: Question out of interest, do you happen to be from India? Some hints in the use of language is why I ask.
Click to expand...

Yes for Question

is there any command to find how much hour it will take?
 

Questa is the top end version. So no speed up from that regard.
But 6.4c? cant you upgrade to a version from the last 5 years? Newer versions might have speed ups (but wont be significant).

Other options:
Dont do gate level simulation (it is much much much much slower than RTL simulation)
Better PC (are you having to use swap memory)?
Better test cases - is there some crazy boot sequence to go through or could skip? Are there any generics like "SIM_SPEED_UP"
interfaces - do you need the full featured crazy timing accurate simulation model? will a behavioural model do? These can often be massive causes of slowdown.
 
TrickyDicky said:
Questa is the top end version. So no speed up from that regard.
But 6.4c? cant you upgrade to a version from the last 5 years? Newer versions might have speed ups (but wont be significant).

Other options:
Dont do gate level simulation (it is much much much much slower than RTL simulation)
Better PC (are you having to use swap memory)?
Better test cases - is there some crazy boot sequence to go through or could skip? Are there any generics like "SIM_SPEED_UP"
interfaces - do you need the full featured crazy timing accurate simulation model? will a behavioural model do? These can often be massive causes of slowdown.
Click to expand...

Still running

Current Time: 8 962 278 880 ns
I started my simulation at morning 10.00 AM(10/19/2014) , Current Time 12.00 AM(10/20/2014)

Still it will take time?
 

8.9 seconds of simulated time? Are you sure your ns units are correct and it's not ps. What are you trying to simulate? I can believe that the evaluation version of Modelsim would take 14 hours to run 8.9 ms. I've seen upwards of 12 hours to run 600 ms of simulation time using Modelsim SE (paid) on a 2.8GHz Xeon workstation with a very large design.

If you have to run a simulation for that long it's typically just better to create an FPGA bit/pof file and test it on the hardware with chipscope/signaltap
 
ads-ee said:
8.9 seconds of simulated time? Are you sure your ns units are correct and it's not ps. What are you trying to simulate? I can believe that the evaluation version of Modelsim would take 14 hours to run 8.9 ms. I've seen upwards of 12 hours to run 600 ms of simulation time using Modelsim SE (paid) on a 2.8GHz Xeon workstation with a very large design.

If you have to run a simulation for that long it's typically just better to create an FPGA bit/pof file and test it on the hardware with chipscope/signaltap
Click to expand...

Currently doing my Graduate Project Title "New Timing Error-Detecting Sequential(EDS) Design for Improved Path Delay Fault Coverage and speedpath Identification Efficiency"

I want to get results on "Run VCS simulation reading in a SDF file to simulate the IU(Integer Unit) with C programs. find the number of clock cycles and timing error coverage"

I am using modelsim for running VCS simulation reading in a SDF file
commands in modelsim used:
1. do compile.do
2.vsim tb_func32 -do "run -all" (I got stuck here)
3.vsim -t ps -sdfmin /tb_msp=final.sdf -c tb_msp

is there any other way to run VCS simulation reading in a SDF file?
 

I think you need to explain what you mean by VCS simulation. The only VCS I know of is Synopsys Verilog Compiler Simulator, which is not Modelsim. If you're using modelsim then you aren't doing a VCS simulation.
 

ads-ee said:
I think you need to explain what you mean by VCS simulation. The only VCS I know of is Synopsys Verilog Compiler Simulator, which is not Modelsim. If you're using modelsim then you aren't doing a VCS simulation.
Click to expand...

OK, thanks you very much

can you explain me how to do VCS simulation reading a SDF file by using SYNOPSYS
 

abu9022 said:
can you explain me how to do VCS simulation reading a SDF file by using SYNOPSYS
Click to expand...

Since you are currently using Questa, first steps would be installing the appropriate software and getting a valid license. Or if that is already installed for you on the department workstation, then you read the starter guide / tutorial for that simulator. At least, that's how I would go about it...

But you already have Questa, which is a pretty darn good simulator IMO. Why bother changing it to VCS simply because some funny person in the past said to use VCS. "Because we have always done it like that"?

And besides, what do you think using VCS is going to do for you? Unfortunately it will not magically make this type of simulation go faster. Anyways, you are of course free to pick whatever simulator you like. The only thing I am saying is to be aware of your motivations for doing so.

VCS is going to be juuuust as slow as Questa, possibly even a bit slower. Or a bit faster, who knows.

If you really do want to spend time changing software, I would suggest using a version of Questa a bit more in line with the year 2014. Questa/modelsim was up to version 10.something last time I looked. Maybe it's even up to 11.x by now... But to be fair, I would not expect huuuge speedups there either. Just that should you feel the need to flush time changing software, flush it there. At least you get some other nice features that were added between now and what version was it? 6.x? 6.4c ... mmmh, I wonder what year that was from. Looks to be 2009-ish...

On the other hand, from a learning perspective it wouldn't hurt to try another simulator. Then you can see for yourself what is useful and what is not so useful about this change.
 

mrflibble said:
Questa/modelsim was up to version 10.something last time I looked. Maybe it's even up to 11.x by now...
Click to expand...

10.3d came out last week. 10.4 is in beta, which apparently will support multi-threading!
 

TrickyDicky said:
10.3d came out last week. 10.4 is in beta, which apparently will support multi-threading!
Click to expand...

Mmmh? Doesn't the current version already support multi-threading? Or is this some windows vs linux difference?

- - - Updated - - -

Do you have a link to the added multi-threading feature in 10.4?
 

mrflibble said:
Mmmh? Doesn't the current version already support multi-threading? Or is this some windows vs linux difference?
Click to expand...

Multi threading an HDL is actually tricky as you have to ensure signals are updated at the correct times. I think you'll need some analysis of the code to check for which signals interact with which other signals to see how you can separate the threads out. But afaik, modelsim never has been multi threaded. The win vs linux thing was 64 bit support (linux had 64 bit first, but the 32 bit always ran faster which mentor even admitted).

Do you have a link to the added multi-threading feature in 10.4?
Click to expand...

Sorry no, as it's what I heard from a colleague giving 10.4 a whirl (but it doesnt have fixes for my latest defects).

Anyway, we're going OT....
 

TrickyDicky said:
Multi threading an HDL is actually tricky as you have to ensure signals are updated at the correct times. I think you'll need some analysis of the code to check for which signals interact with which other signals to see how you can separate the threads out. But afaik, modelsim never has been multi threaded. The win vs linux thing was 64 bit support (linux had 64 bit first, but the 32 bit always ran faster which mentor even admitted).



Sorry no, as it's what I heard from a colleague giving 10.4 a whirl (but it doesnt have fixes for my latest defects).

Anyway, we're going OT....
Click to expand...

what will happen if i write run 100ns instead of run -all in the following command

vsim tb_func32 -do "run -all"
 

run -all will run till the simulation no longer has any signals making transitions or it finds some control statement that stops/halts the simulation.

run 100 ns will run for 100 ns and stop.
 

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