lockup latch hold issue

hi,
I have a case where the scan stitching needs to be done between 2 async clock domains. I know that we need negative latches as lockup latches when we stitch two posedge triggered flops from asynch clock domains. My question is, for this particular case in the figure, is the hold time meeting for the capture clock? 1,2,3 represent the time when the negative level starts for the latch.

By adding the latch, we only 'hope' to meet the hold time requirements of the capture flop by reducing the hold path length. If required the tool will probably still have to add a few delay buffers between the latch and the capture flop if hold analysis indicates violations in that path.

1)without the latch the hold path is from launch flop (edge 1 in your figure) to capture flop edge + its hold time,
2) with the latch it is (in worst case) from edge 2 (falling edge of 'neg edge lockup latch' of your figure) to the same capture edge + hold time as before

The path in 2) is less long than 1), and thus the tool can find it easier to close hold timing for capture flop.
Note: by worst case in 2) above, I mean that the data lands up at the latch before or right when its goes enabled (edge 2). It could well arrive after the latch is enabled, in which case it would be even easier for the tool to meet hold for the capture flop. There are a few articles written on how this case is analysed for timing by dividing the path into 2: one between the source flop and the latch and the other between the latch and capture flop, I highly recommend reading those.

I have a counter question though: why isn't a synchronizer added b/w these 2 asynchronous domains while stitching scan chains in DFT? How is metastability prevented?

Hi Vijay82, I don't have knowledge about DFT. The only thing that I understood after reading some articles was that we use lockup latches for dft when we are stitching flops from domains where no logical paths exist. That is when this question popped in my mind.

Without schema and comp. specs, I can't tell, but if this is a parallel clock FF with Qbar out, then yes most logic familes have zero hold time but positive setup time.

This permits synchrpnous shift registers to work and sync counters to work.

Depending on family, HC, LV LVC2, ECL, the setup and hold times all vary.

edge Sensitive is preferred over level sensitive latches to,avoid dead time or alaising effects of sampling....