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Verilog multi dimensional array

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Which is the right way of declaring a multi dimensional array reg [1:0] variable [N-1:0] or reg [1:0] variable [0:N-1] ? What difference does it make whether you declare it one way or the other?
 

If you only access the unpacked dimension (the range to the right of the variable) one element at a time, the only difference it makes is if you use $readmem to load the memory from a file, the left range index gets loaded first.

There can be more of a difference in SystemVerilog because it deals with streams of bits that span more than a single element.
 

Thanks for the reply Dave.

The variable I'm talking about is inside a memory model used for simulations. If I use [N-1:0] form instead of the other in my model will it give erroneous results during simulation? I'm not loading the mem using $re
 

The difference between [N-1:0] and [0:N-1] should not make any difference if you only access one indexed element of a dimension at a time. That is true for any dimension. Are you seeing something that make you think otherwise?
 

i have faced the same problem before but when i declare both as a packed array but in unpacked array error may due to trying to equaling or comparing the two arrays or display the hole array not one element a time.
 

With the exception of $readmem, Verilog does not allow you to access more than one unpacked array element at a time. SystemVerilog allows you to copy and compare whole unpacked arrays having the same shape. It also has the "%p" format for displaying aggregate data like unpacked arrays.
 

the right way of declaring a multi dimensional array is reg [1:0] variable [0:N-1]. This is the general structure.. It means that the two bits array of N elements have been declared starts from 0 to N...
 

There is no right way here. It is just what conventions people are used to.
 

yes dave_59 most probably the memory array used as reg [1:0] variable [0:N-1]. so only i stated like that.. But actually as your words There is no right way here....
 

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