How to analysis and calculate power on chip level?

Power analysis

Hi all,


Can you tell me good material to analysis and calculate POWER on chip level. In short I need to analyze my design, why it is taking so much power?

Rahul A. Shelke

Power analysis

have a look @


search forum 4 many low power docs

some key tips are

reduce clock and signal toggling.
multi vt design.
reduce memory,registers in design

Re: Power analysis

Hi,

Thank you for the reply but, I don't want the information on tools, but i want some documents on the analysis and calculation of POWER and IR DROP.


Rahul A. Shelke

Power analysis

Rahul ,
did u search the forum, there are lot of docs here already..

Re: Power analysis

Hi whizkid


I am sorry, But I searched the forum but didn’t got any thing what i need. there is lot of suggestion which are very good. But I want some paper for POWER and IR DROP, so that I can read it and get some comfortable position (technically) for my design.


Thank you

Rahul A. Shelke

Re: Power analysis

well LOW POWER VLSI Design is always difficult to analyze when it comes to chip level.. i have some materials.. one good book is by Prof. Anantha P. Chandrakasan is a very good book.I wud say thats the best book avilable.

Low-Power Digital VLSI Design -- This is a good book.

I shall upload some materials which might be helpful.. could u please request a particular topic which i can post.. they are n slide format.

with regards,

Re: Power analysis

Thanks Arun,

I will go for this book, Bcoz I want to settle in the power analysis.

As per you ask for a particular topic, so, I have created a floorplan with power structure, and calculation of POWER is 1.7W (huge). So I want to know the cause of this result.

I think my memories r taking lot of power. Is it the problem of power structure or something else?

Thank you

Regards,

Rahul A. Shelke

Re: Power analysis

well dude.. 1.7W is HUGE! considerin ur workin on micro electronics.. this 1.7W wud kill ur design.

What floorplanner are u using.. am sure memory wud be the main culprit when it comes to such high power problems..I wish you go thru the document am uploading now.. it has all basics of a typical low power design.

Low power CMOS Digital Design by Anantha P Chandarasekaran, Samuel Sheng and Robert W Bordersen, this is a IEEE paper highlitin the basics of low power digital CMOS design.

There is another document which explains abt low power RAM circuits.

with regards,

Re: Power analysis

Thanks Arun,


I am going through your papers, papers are awesome I liked it. Papers having the most of the thing what I was searching for.

Thanks once again

Regards,

Rahul A. Shelke

Re: Power analysis

Hello Arunragavan,
Can you please send me the documents you mentioned for Low power CMOS design?My gmail id is mineheaven@gmail.com.
Thanks in advance

Power analysis

intresting aspect

Re: Power analysis

hi,

I would like to add my 2 cents to your high power.

1. Dump a detailed individual cell contribution on the power, this will give you an idea which cell/memory is using more power and can judge based on this.
check how are you specifing the power numbers for memories, either you are feeding the real power values are asking the tool to auto understand the power pads and then extract the memory power network... check this.
2. If you are using static IR drop analysis, then check out your clock frequencies values and their respective activity numbers, in case if you have not specified any such activity numbers, then by default, the tool would assume a very pessimistic number(which in reality might now happen) at all...(this could really help to sort out your problem).
3. For the cells which are highly power hungry, check your library for this.


happy designing.
https://www.vlsichipdesign.com

Power analysis

very good! This topic is very important in the VLSI design with the growth of gate-count!

Power analysis

Hi i have a question. During the power plan stage of my design I was getting this warning saying unconnected nets. and majority of them were at IO pads. Though I could not see where I was goin wrong as I had done everything properly from the FP stage

Added after 1 minutes:

Can anyone tell what might had gone wrong. I had redone everything from FP, powerplan, sroute but still same warnings came. please help