dpaul
Advanced Member level 5
Hi all,
I am trying to simulate a uP core defined in sv using Xilinx Vivado suite.
However I get an error message for which I cannot find a fault.
This error message points to the part of the code as below:
Note that in the above error line, the variable 'dmem_rd_check_size' is allocated to type 'type_operation_mode_e'.
I have the 'type_operation_mode_e' defined in an `include file as follows:
I have checked this entire file/code and no where is there an illegal assignment for 'dmem_rd_check_size'.
Then why is the Vivado simulator throwing such an error?
I have hit a wall. Please help or advice.
I am trying to simulate a uP core defined in sv using Xilinx Vivado suite.
However I get an error message for which I cannot find a fault.
This error message points to the part of the code as below:
Code:
`ifdef MPU_EN
output logic [ ARCHITECTURE_BASE-1:0] dmem_rd_check_addr,
output type_operation_mode_e dmem_rd_check_size, <-- ERROR line
`endifNote that in the above error line, the variable 'dmem_rd_check_size' is allocated to type 'type_operation_mode_e'.
I have the 'type_operation_mode_e' defined in an `include file as follows:
Code:
typedef enum logic [1:0] {
DATA_MODE_BYTE,
DATA_MODE_WORD,
DATA_MODE_DWORD,
DATA_MODE_X=2'bxx
} type_operation_mode_e;I have checked this entire file/code and no where is there an illegal assignment for 'dmem_rd_check_size'.
Then why is the Vivado simulator throwing such an error?
I have hit a wall. Please help or advice.
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