gabrielbertotti
Newbie level 3
Dear all,
I hope this is the right place to ask for your opinion.
I'm designing a mixed signal ASIC and I'm wondering which could be the best design flow for my case.
I'm new to mixed signal but I've already taped out a few analog chips and I can manage to synthetize and
layout (with SoC encounter) small digital blocks.
My Chip has only one big analog block which however only needs power supply, bias voltages and
has a very simple digital interface (It is an array of ADCs that give out the result of on-chip measurements).
I should now implement a digital block that interfaces this analog block with the pads, do some data processing
and is able to handle a very high data stream.
I looked in interned and it seems I could do one of the following:
1) Floorplan with Virtuoso Layout for creating a soft block for the digital part. Import this soft block in SoC
Encounter and create the layout. Export to OA and back in Virtuoso put the analog, digital and pads together
with manual routing.
2) Write a VHDL top cell with analog block, digital block and pads. Import in SoC encounter, layout and export.
Which is preferable? Or are there some other ways?
The 2) seems easier, however I still have some problems with the analog block in SoC encounter, while in 1) the
effect of the pads on the digital interface can be estimated only at spectre level after total parasitic analog extraction
- which cannot then be simulated, since the chip is too complicated.
For any hit, many thanks to all of you,
regards
Gabriel
I hope this is the right place to ask for your opinion.
I'm designing a mixed signal ASIC and I'm wondering which could be the best design flow for my case.
I'm new to mixed signal but I've already taped out a few analog chips and I can manage to synthetize and
layout (with SoC encounter) small digital blocks.
My Chip has only one big analog block which however only needs power supply, bias voltages and
has a very simple digital interface (It is an array of ADCs that give out the result of on-chip measurements).
I should now implement a digital block that interfaces this analog block with the pads, do some data processing
and is able to handle a very high data stream.
I looked in interned and it seems I could do one of the following:
1) Floorplan with Virtuoso Layout for creating a soft block for the digital part. Import this soft block in SoC
Encounter and create the layout. Export to OA and back in Virtuoso put the analog, digital and pads together
with manual routing.
2) Write a VHDL top cell with analog block, digital block and pads. Import in SoC encounter, layout and export.
Which is preferable? Or are there some other ways?
The 2) seems easier, however I still have some problems with the analog block in SoC encounter, while in 1) the
effect of the pads on the digital interface can be estimated only at spectre level after total parasitic analog extraction
- which cannot then be simulated, since the chip is too complicated.
For any hit, many thanks to all of you,
regards
Gabriel