Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Lockup Latch during capture

Status
Not open for further replies.

priyutiru

Newbie level 5
Joined
Dec 15, 2013
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,338
Hi,

Lockup latches can help in hold time violation during scan shift. How about during Capture?

Thanks
 

Lockup is between one flop's Q pin to another's SI pin. It doesn't play a role in capture stage.
 

During capture, design is in functional mode, hold time violation is solved by STA team during Functional timing closure.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top