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11th August 2014, 18:27 #1
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What are betaeff and vdsat parameters found from Cadence simulation
Hi.
Can you please tell me the interpretation of the betaeff and vdsat parameters obtained from Cadence ADE simulation using "Results > Print > DC Operating Points" ?
I am asking this because in a simulation of mine, the displayed results are as below:
betaeff 3.837mThis shows that:
...
ids 13.55u
...
vdsat 113.3m
vgs 1.164
vth 1.104
1. the shown vdsat is not equal to (vgsvth) !
2. using the equation: ids=(beta/2)*(VgsVth)ē and using the shown betaeff, the result is ids=6.9u, while the display result is 13.55u, is it that the displayed bettaeff=(beta/2)?
N.B. Rephrasing a very old post to get any fresh view if possible!

11th August 2014, 21:13 #2
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Re: What are betaeff and vdsat parameters found from Cadence simulation
In old CMOS processes, where the square law was a good approximation, vdsat should indeed be equal to vgsvth when the transistor is in strong inversion and channel modulation can be ignored (long L). In your case the transistor is in moderate inversion as vgs is almost equal to vth. Try to make vgs a little higher and then recheck vdsat.
In modern CMOS processes, the square law (ids=(beta/2)*(VgsVth)ē) is not a good approximation anymore. E.g. due to velocity saturation, vdsat is not equal anymore to vgsvth.

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12th August 2014, 05:27 #3
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Re: What are betaeff and vdsat parameters found from Cadence simulation
Ok, so, using the square law equation is an approx. in respect of modern tech. is what u mean to say  thanks.
Can you please tell what does the betaeff and vdsat parameters obtained from Cadence ADE simulation stand for i.e., meaning of these?

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12th August 2014, 09:02 #4
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Re: What are betaeff and vdsat parameters found from Cadence simulation
Do you have the book of Razavi? You can find a formula for the VDSsat for processes where L<1um in chapter 16.2.3
Vdsat is the VDS were the transistor enters the saturation region, so it is very useful in e.g. amplifiers were you want to have your transitors in saturation for linearity.
I never use betaeff, i don't know a use for them since the square law is not valid in submicron processes.
For your own understanding, you could plot id vs VDS for different VGS and check the vdsat parameter from spectre with the vdsat that you can find from the graph.
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12th August 2014, 11:53 #5
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Re: What are betaeff and vdsat parameters found from Cadence simulation
Thanks beetwee. I got the meaning of Vdsat :)
Actually, I wanted to know the significance of betaeff because I need to know the value of (u*Cox) of a MOSFET in a particular tech for designing a circuit  Can you pls help with how to determine the (u*Cox) in Cadence?

12th August 2014, 13:31 #6
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Re: What are betaeff and vdsat parameters found from Cadence simulation
betaeff should be equal to mu0*Cox*W/L. But because the square law is only a rough approximation in modern processes, it is hard to determine the exact value of mu0Cox because Cadence uses a more complex model of a transistor. So don't expect 100% matching results between hand calculations and simulation results! I think that the error between hand calculations and simulations will be smallest if you choose a large L (410 times minimum L)
What process do you use?

12th August 2014, 14:11 #7
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Re: What are betaeff and vdsat parameters found from Cadence simulation
I am using UMC 180nm process.
I want to know the (mu0*Cox) of the NMOS and PMOS which are required in hand calculations towards designing an opamp.
Can I take the betaeff reported by Cadence, divide it by whatever (W/L) present in the schematic, and use the result as the (mu0*Cox) of the MOSFETs?

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12th August 2014, 16:48 #8
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Re: What are betaeff and vdsat parameters found from Cadence simulation
For hand calculation around 1020% of accuracy isn't a problem, especially for CMOS nodes older than 130nm, so if You want to working in strong inversion, a square law s+hould be ok and quite accurate if Vds/L < 0.8MV/m for nmos and 1.95MV/m for pmos (values of critical field E_C).
If You really want to obtain good accuracy You should use one of the physical models, i.e. EKV or ACM which are quite easy to use
In saturation region drain current is described by formula:
where I_spec is a specific current for given technology and mosfet dimensions and in EKV is given as (in ACM factor 0.5 exists instead of 2):
and i_f is a normalized drain current which is bounded with normalized charge in channel by following relation:
,
while q_f is given by Lambert W function:
The K is current gain factor K=ĩCox and every effects with higher vertical/longitudinal field and series resistance is modeled as a factor in K:
where is constant in order of 1e7/tox, E_C is above, \beta is equal 2 for nmos and 1 for pmos fets, Rs=Rd for rectangular transistors and is equal to contact resistances (parallel connection of vias at drain and source).
The DIBL You can modeled by varying the threshold voltage:
where \lambda is a "characteristic length" defined in Tsividis book about modelling (factor of many technological constants)
Using above equation You are able to solve it for given properties by hand (or by Mathemitaca tool ) or by some numerical calculations in C, python or other language.
If You really want to study about mosfet modelling, check papers about EKV, ACM models and also about BSIM6 which are develope from EKV.
Some links:
http://www.sciencedirect.com/science...38110111003492
http://ieeexplore.ieee.org/xpls/abs_...=6343331&tag=1
http://ieeexplore.ieee.org/xpls/abs_...number=6632892
http://www.sciencedirect.com/science...26269214001323Last edited by Dominik Przyborowski; 13th August 2014 at 11:09.
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30th April 2015, 04:27 #9
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