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Vivado warning during place design [Constraint 18-96]

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Hello all,

I've scanned the web & can't find a single item on this.

I'm working with some legacy code & moving into a Kintex 7 device

There is a constraint in the legacy ucf
Code: 
OFFSET = IN 4ns BEFORE "ATA_IORDY"

Therefore I thought...I should move this same constraint to my new .xdc

Code: 
 set_input_delay 4 ATA_IORDY

maybe i need a [get_ports ATA_IORDY], anyway....

The warning message i get regarding this is

[Constraints 18-96] Setting input delay on a clock pin 'ATA_IORDY' is not support, ignoring it.
Click to expand...

Seriously whats that all about. There is nothing on the web about this "[Constraints 18-96]".

I thought of posting this on xilinx website...but their forums aren't as good as this one.

Many Thanks for any help

Regards,
Wesley
 

I commiserate with you, I've also been suffering from the lack of explanation of error/warning messages for Vivado. You probably should ask stuff like this on Xilinx's forum as factory FAE types spend time answering questions on that forum.

Have you looked at the design to see where ATA_IORDY goes? If it's used in any edge detecting code line rising_edge (ATA_IORDY) or always @(posedge ATA_IORDY) then it will be ignored for set_input_delay constraint as you would add any "offset" delays for a "clock" in the create_clock command (Yeah, I know ATA_IORDY is not actually a clock, but the original designer made it a clock :p).

Regards
 

i think the syntax is
set_input_delay –<to what clock> <time> [get_ports <port name>]

by set_input_delay 4 ATA_IORDY

you try to set input delay to ATA_IORDY clock rather then the data registered by this clock
 

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