Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

clock frequency in hold time

Status
Not open for further replies.
R

rakesh@981

Newbie level 1
Joined
Aug 6, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
6
why hold time is not consider for clock frequnecy calculations?
 

Because Hold time check is on the same clock edge. Clock slow or fast won't affect the result.
 

When you consider clock-Q delay and the combi delay. the hold time is already present in that window. Think about it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top