skoda
Junior Member level 3
Hi,
I try to design symmetrics ota ( Sansen page 216 ), I use gm/id methodology ( i have learn it from D.M. Binkley tradeoffs), so a use this equation :
W/L= (1/IC) * (Idrain/Io) but when i need to design transistor Nmos for 25nA and IC=10, a will get W/L=1/256 which introduce me into problem with min. lenght which i have calculated by: Lmin= Wmin*L/W = 102.4u. Anyway cadence return me error because i have wrong Lmin or Lmax or Wmin Wmax.
(Io i mean technological current for 0.18um)
So is this methodology still propper for such low current? Please help to small student from Czech Republic .
I try to design symmetrics ota ( Sansen page 216 ), I use gm/id methodology ( i have learn it from D.M. Binkley tradeoffs), so a use this equation :
W/L= (1/IC) * (Idrain/Io) but when i need to design transistor Nmos for 25nA and IC=10, a will get W/L=1/256 which introduce me into problem with min. lenght which i have calculated by: Lmin= Wmin*L/W = 102.4u. Anyway cadence return me error because i have wrong Lmin or Lmax or Wmin Wmax.
(Io i mean technological current for 0.18um)
So is this methodology still propper for such low current? Please help to small student from Czech Republic .