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Using VHDL generic and configuration after synthesys to verilog netlist

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Using VHDL generic and configuration after synthesis to verilog netlist

Hi all,

Actually, all of my designs is VHDL file and use 'generic' and 'configuration' features.
Although I synthesized VHDL files to the verilog netlist, test bench files are still VHDL.
You know, sysnthesis tools such as DC don't support 'generic' and 'configuration'.

My question is how can I use only one test bench file in case of both RTL simulation and gate-level netlist simulation.
The most simple solution is just deleting generic and configuration lines in gate-level simulation. But I want use this tb in case of RTL sim(VHDL) and gate-level sim(verilog) like as '#ifdef' in C language.

For example, following code is part of a VHDL test bench.
Code VHDL - [expand]
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INST1 : TOP_MODULE
        generic map(
        length => 5
    )
        .....
        configuration CFG_TB of TB is
        for behavior
            for INST1: TOP_MODULE
                use configuration WORK.CFG_TOP_MODULE;
            end for;
        end for;
    end  CFG_TB;


Thanks.
 
Last edited:

We face this issue during multiple projects, to solve, that we have two top_tb:
1- RTL code with generic and the test-bench.
2- netlist and the same test bench.

Then you could run the same simulations.
 

Why are you talking about DC. I don't understand. As rca has pointed out, the same testbench should be sufficient.
 

rca said:
We face this issue during multiple projects, to solve, that we have two top_tb:
1- RTL code with generic and the test-bench.
2- netlist and the same test bench.

Then you could run the same simulations.
Click to expand...

You are right. I could make two seperate top_tb, but I just want a way using only one test bench.
Maybe, there is no other way.
Thanks.

- - - Updated - - -

After synthesis using DC, some VHDL features such as generic, configuration is removed.
That's why I refered to DC. Because verilog netlist don't have generic and configuration, the same VHDL testbench will not be compiled.
I think rca's method is right answer. But I just want to more simple way to use only one testbench.
Maybe... there is no another way...
Thanks.
 

You could just create a wrapper file that does have the generics and instantiates the netlist.
 

You will used the same test-bench, only the top_tb made the connection, the test-bench remains the same for both targets.
 

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