Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Using PTM model in hspice and measuring the leakage power of bulk cmos and finfet(DG)

Status
Not open for further replies.

loves86137

Newbie level 3
Joined
Jul 14, 2014
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
35
Hi,everyone:
Could you give me a hand to solve following questions?

(1)I download the predictive technology model for 32nm finfet(double-gate) technologies from the website (http://ptm.asu.edu) ,but I found one of the files , 32nm_finfet.pm, which described the double-gate used two parallel connection transistors, like this:

擷取.PNG

Is it true? Because I think the double-gate finfet isn't just parallel two transistors.

(2)I also download the 16nm finfet model(PTM-MG) and the 16nm cmos model(PTM LP model) ,and then measuring the leakage power and total power. I found the total power of 16nm cmos is far less than the total power of finfet ,is it true? And I measured the leakage power of cmos is similar to the leakage power of finfet. This is my spice file. By the way, I browsed this website(https://www.edaboard.com/threads/202213/), but I don’t know whether I need to download bsim cmg model files? I do download this file, but I don’t know how to operate it. Now I use include .pm file to run the hspice model.

View attachment spice.7z

(3) how could I exactly measure the leakage power of hspice? As so far, I enter the input to keep it stable and look the power figure. Plazzzzzzz give me a hand to solve my problems. Finally, thank you for your reading.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top