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Dynamic power is reduced when I increased frequency

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makanaky

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Hi,

I am designing a digital filter . First it was using 3 multipliers working at frequency x . So I increased the multiplier frequency to be 3x in order to use 1 multiplier. I found that after doing this, the dynamic power is reduced to 1/3.

I cannot understand how did this happen ? Isnt Pdynamic= C*Vdd^2*f

So the multiplier power should be increased by factor 3, and since I am using 1 instead of 3, then the overall power should be approximately the same in both cases ?

Please let me know what's wrong with my above analysis

Thanks
 

Hi,

i´m not familiar with ASIC design.

your formula
P = C*Vdd^2*f
isn´t that some kind of average power?

My idea is: Multiplyer is a clocked process. With the clock edges all states change and after some nanoseconds the result is fix.
So the high current last only some ns. after this time the current drops to an idle value.

External power supply capacitors act like a low pass filter and you will see the average current C * Vdd * f
But internal of the asic you will see a high current peak lasting only some ns with an amplitude. Let´s name it I_mul. This i´d call peak current for one multiplication.

If you now use three of these multipliers at exactely the same clock edge, then you may expect a peak current of 3 x I_mul.
But since you use this only once instead of three times a single multiplication i´d expect the average current to be about equal.

In my eyes it´s the question how the dynamic power is defined.
If it is the peak current (I_mul) then it makes sense that it drops to 1/3.

Klaus

Edit/added: I know i mixed up power and current. But as voltage is constant the power is proportional to current. I hope everyone knows what i mean...
 

KlausST said:
Hi,

i´m not familiar with ASIC design.

your formula
P = C*Vdd^2*f
isn´t that some kind of average power?

My idea is: Multiplyer is a clocked process. With the clock edges all states change and after some nanoseconds the result is fix.
So the high current last only some ns. after this time the current drops to an idle value.

External power supply capacitors act like a low pass filter and you will see the average current C * Vdd * f
But internal of the asic you will see a high current peak lasting only some ns with an amplitude. Let´s name it I_mul. This i´d call peak current for one multiplication.

If you now use three of these multipliers at exactely the same clock edge, then you may expect a peak current of 3 x I_mul.
But since you use this only once instead of three times a single multiplication i´d expect the average current to be about equal.

In my eyes it´s the question how the dynamic power is defined.
If it is the peak current (I_mul) then it makes sense that it drops to 1/3.

Klaus

Edit/added: I know i mixed up power and current. But as voltage is constant the power is proportional to current. I hope everyone knows what i mean...
Click to expand...

Thanks Klaus , but you missed that in the 1st case the frequency is x and in the 2nd the frequency is 3x ... so in period 1/x -> the 2nd case will have 3 peaks for current also (at the beginning of each of the 3x clock), right ?
 

First, you estimate is right that the your average power dissipation should be equal. Before getting into the details, how are you exactly measuring power. Is this an HSPICE simulation? Can you check your total current and see how that has changed between the two designs?
 

Hi,

with myidea the peak current is independent of frequency. It is the current that is needed to change all logic states for the multiplier within the few ns.
(but it depends whether the multiplier is 16 bits wide or 32 bits wide)

The value of the current peak is the same independent if it is called once per ms or once per ns.
The average will surely change...

but to be true - it is only an idea..


Klaus
 

saurabhr8here said:
First, you estimate is right that the your average power dissipation should be equal. Before getting into the details, how are you exactly measuring power. Is this an HSPICE simulation? Can you check your total current and see how that has changed between the two designs?
Click to expand...

These are post synthesis results using Cadence RTL compiler
 

makanaky said:
Hi,

I am designing a digital filter . First it was using 3 multipliers working at frequency x . So I increased the multiplier frequency to be 3x in order to use 1 multiplier. I found that after doing this, the dynamic power is reduced to 1/3.

I cannot understand how did this happen ? Isnt Pdynamic= C*Vdd^2*f

So the multiplier power should be increased by factor 3, and since I am using 1 instead of 3, then the overall power should be approximately the same in both cases ?

Please let me know what's wrong with my above analysis

Thanks
Click to expand...

You have replaced 3 multipliers with one running at 3 times the rate. 1/3 the multipliers -> 1/3 the capacitance. It appears that your tool identified the reduced capacitance but did not identify the increased frequency. Perhaps the estimate is calculated for some default frequency.
 

Hi,
The toggle rates/switching factors used for both cases may be different . If you do not specify the toggle rates, the Synthesis tool will use an estimate toggle factor , for Power estimation.

Also check if u have applied the correct timing constraint.
 

Do you have any self biased CMOS buffers in the filter?

If no analog losses then the dynamic loss should increase from capacitive load current transition rate. A 50mV current shunt in the right place will confirm your expectations for test purposes only.
 

1- the dynamic power: as indicate it is dynamic means versus time, to compare two architectures, you need to execute the same jobs at the same rate. When I read the QOR report of Cadence RTL compiler, I don't see any timing information?

2- when we design a digital filter we look to have the maximum of cycles where the multiplier is used, I means if you need to do 15 mutiplications every 4 clock cycles, you should be able to organise your filter to used only 4 multipliers.
 

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