u24c02
Advanced Member level 1
Hi.
When i have trying to use these signal and variable in vhdl, i dont know exactly different each of them.
What they have pros and cons and how can handle to use? Would you let me know?
When i have trying to use these signal and variable in vhdl, i dont know exactly different each of them.
What they have pros and cons and how can handle to use? Would you let me know?