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9th July 2014, 08:46 #1
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calculation the delay time of symmetric load delay cell
hi
I want to calculate delay time for this cell with analytic equation and software, but I don't know how I do this
I would be glad if anyone help me to do this

10th July 2014, 09:07 #2
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Re: calculation the delay time of symmetric load delay cell

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12th July 2014, 09:07 #3
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Re: calculation the delay time of symmetric load delay cell
dont have any idea??

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17th July 2014, 18:51 #4
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Re: calculation the delay time of symmetric load delay cell
:(:(:(:(:(

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17th July 2014, 22:02 #5
Re: calculation the delay time of symmetric load delay cell
Delay time by the definition is the time between when the input crosses its 50% of final value and when the output crosses its 50% of final value. In order to calculate (or simulate) the delay time, a step input should be put in the input and calculate (or measure) the time between two mentioned crossings.
The circuit is generally nonlinear, so you can not use half circuit approach. In order to calculate precise delay, it's necessary to observe transistors in different moments of transaction and write correct formulas considering transistors' working regions. It could be a tough job, however there may be some approximate solutions.
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18th July 2014, 12:05 #6
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Re: calculation the delay time of symmetric load delay cell

18th July 2014, 15:32 #7
Re: calculation the delay time of symmetric load delay cell
Start by making some simplifying assumptions. Your circuit can be modeled as the following picture:
Assume that for a long time before t=0:
Vin+=0 and Vin=Vdd
and after t=0:
Vin+=Vdd and Vin=0
Then continue writing equations and determine what happens for (Vout2Vout1).
I can't help further because doing a complete analyze is in the scope of a research paper!
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18th July 2014, 19:19 #8
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18th July 2014, 20:11 #9
Re: calculation the delay time of symmetric load delay cell
The resistors are not necessarily linear, actually, I meant that solving the above circuit can help you have an idea about your own circuit.
Becoming curious I found this paper:
"LowJitter ProcessIndependent DLL and PLL Based on SelfBiased Techniques"
by John G. Maneatis
That's all you want
As you know, I can't put it here.
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