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Using XADC with ZYBO7000

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bene_

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Hi,

I have a Zybo7000 Development Board from Digilent, which contains a ZYNQ XC7Z010-1CLG400C from XILINX. I'm now trying to access the XADC of the FPGA via the DRP using the XILINX XADC wizzard to convert an external analog voltage. However, I run into problems since I'm not able to successfully instanciate the XADC together with the xdc file. Did anybody ever use the XADC from these FPGAs?

To access the XADC I need to manually insert a differential input buffer IBUFDS_DIFF_OUT, since my synthesis tool Vivado is not able to do this automatically. The I/O standard I set for these pins is "DIFF_HSTL_II_18" since apparently an analog input standard is not available and any differential input standard should work.

From the implementation I get the following critical warnings:
[Route 35-54] Net: IBUFDS_DIFF_OUT_inst/ob is not completely routed.
[Route 35-54] Net: IBUFDS_DIFF_OUT_inst/o is not completely routed.
[Route 35-54] Net: IBUFDS_DIFF_OUT_inst/ob is not completely routed.
[Route 35-54] Net: IBUFDS_DIFF_OUT_inst/o is not completely routed.
[Route 35-7] Design has 2 unroutable pins, potentially caused by placement issues.
[Route 35-1] Design is not completely routed. There are 2 nets that are not completely routed.
Click to expand...

The bitstream generation quits with the following errors:
[Drc 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem net(s) are IBUFDS_DIFF_OUT_inst/o, IBUFDS_DIFF_OUT_inst/ob.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Click to expand...

I googled a lot but could not find any helpful links. Does anybody have an idea how to successfully instanciate these XADCs?
 
Last edited by a moderator:

I'm pretty sure that I didn't have to add an input buffer of any kind when I used the XADC on a Kintex 7 design (same Vivado tool flow). I do remember there were some specific things that I needed to do to get it to correctly connect the XADC, but I can't recall what it was and I no longer have access to the files form that design (different employer). Unless someone else comes up with the answer, I'll look into this later today.

Regards
 

Hi, since I did not succeed to instantiate the XADC yet, would you have an additional hint of how to do this?
 

Hello, i would be interested in a solution to this problem as well. The schematics for the ZYBO Zynq 7000 Development Board suggest that the VP and VN analog inputs are not connected, so i am trying to use one of the auxiliary input pairs for the ADC.

According to the UG480 XADC User Guide on page 26 under "Auxiliary Analog Inputs" when insantiating the XADC "...The auxiliary analog inputs are automatically enabled when the XADC is instantiated in a design, and these inputs are connected on the top level of the design. The auxiliary analog inputs do not require any user-specified constraints or pin locations. They do not require an I/O standard setting to be added to the UCF or in the PlanAhead pinout tool. All configuration is automatic when the analog inputs are connected to the top level of the design..."

After not specifying any of the above in the xdc file vivado uses for the constraints, i get the following error message during implementation:
Code: 
[Place 30-372] Bank.35 has terminals with incompatible standards:
Incompatible Pair of IO Standards: LVCMOS33 and LVCMOS18
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  Out  Bank: 35 Drv: 12 Placed :
	Term: C86
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
	Term:  VAUXN[0]
	Term:  VAUXN[1]
	Term:  VAUXN[2]
	Term:  VAUXN[3]
	Term:  VAUXN[4]
	Term:  VAUXN[5]
	Term:  VAUXN[6]
	Term:  VAUXN[7]
	Term:  VAUXN[8]
	Term:  VAUXN[9]
	Term:  VAUXN[10]
	Term:  VAUXN[11]
	Term:  VAUXN[12]
	Term:  VAUXN[13]
	Term:  VAUXN[14]
	Term:  VAUXN[15]
	Term:  VAUXP[0]
	Term:  VAUXP[1]
	Term:  VAUXP[2]
	Term:  VAUXP[3]
	Term:  VAUXP[4]
	Term:  VAUXP[5]
	Term:  VAUXP[6]
	Term:  VAUXP[7]
	Term:  VAUXP[8]
	Term:  VAUXP[9]
	Term:  VAUXP[10]
	Term:  VAUXP[11]
	Term:  VAUXP[12]
	Term:  VAUXP[13]
	Term:  VAUXP[14]
	Term:  VAUXP[15]

Incompatible Pair of IO Standards: LVCMOS18 and LVCMOS33
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
	Term:  VAUXN[0]
	Term:  VAUXN[1]
	Term:  VAUXN[2]
	Term:  VAUXN[3]
	Term:  VAUXN[4]
	Term:  VAUXN[5]
	Term:  VAUXN[6]
	Term:  VAUXN[7]
	Term:  VAUXN[8]
	Term:  VAUXN[9]
	Term:  VAUXN[10]
	Term:  VAUXN[11]
	Term:  VAUXN[12]
	Term:  VAUXN[13]
	Term:  VAUXN[14]
	Term:  VAUXN[15]
	Term:  VAUXP[0]
	Term:  VAUXP[1]
	Term:  VAUXP[2]
	Term:  VAUXP[3]
	Term:  VAUXP[4]
	Term:  VAUXP[5]
	Term:  VAUXP[6]
	Term:  VAUXP[7]
	Term:  VAUXP[8]
	Term:  VAUXP[9]
	Term:  VAUXP[10]
	Term:  VAUXP[11]
	Term:  VAUXP[12]
	Term:  VAUXP[13]
	Term:  VAUXP[14]
	Term:  VAUXP[15]
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  In   Bank: 35 Placed GClock :
	Term:  and CLK125M
Code: 
[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |     9 | LVCMOS33(9)                                                            |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |    34 | LVCMOS33(2)  LVCMOS18(32)                                              |                                          |        |  +1.80 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   100 |    43 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | A0                   | LVCMOS33        | IOB_X0Y31            | U17                  |                      |
|        | CS1_N                | LVCMOS33        | IOB_X0Y43            | V13                  |                      |
|        | KEY1_KEY             | LVCMOS33        | IOB_X0Y27            | U15                  |                      |
|        | KEY2_KEY             | LVCMOS33        | IOB_X0Y8             | V17                  |                      |
|        | LED_A                | LVCMOS33        | IOB_X0Y35            | Y17                  |                      |
|        | RESET_KEY            | LVCMOS33        | IOB_X0Y7             | V18                  |                      |
|        | RES_N                | LVCMOS33        | IOB_X0Y42            | V12                  |                      |
|        | SCL                  | LVCMOS33        | IOB_X0Y13            | W16                  |                      |
|        | SI                   | LVCMOS33        | IOB_X0Y10            | T17                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | C86                  | LVCMOS33        | IOB_X0Y50            | J15                  |                      |
|        | CLK125M              | LVCMOS33        | IOB_X0Y78            | L16                  |                      |
|        | VAUXN[0]             | LVCMOS18        | IOB_X0Y97            | B20                  |                      |
|        | VAUXN[10]            | LVCMOS18        | IOB_X0Y83            | M18                  |                      |
|        | VAUXN[11]            | LVCMOS18        | IOB_X0Y79            | J19                  |                      |
|        | VAUXN[12]            | LVCMOS18        | IOB_X0Y69            | F20                  |                      |
|        | VAUXN[13]            | LVCMOS18        | IOB_X0Y63            | G20                  |                      |
|        | VAUXN[14]            | LVCMOS18        | IOB_X0Y57            | N16                  |                      |
|        | VAUXN[15]            | LVCMOS18        | IOB_X0Y51            | J16                  |                      |
|        | VAUXN[1]             | LVCMOS18        | IOB_X0Y93            | D18                  |                      |
|        | VAUXN[2]             | LVCMOS18        | IOB_X0Y85            | M20                  |                      |
|        | VAUXN[3]             | LVCMOS18        | IOB_X0Y81            | L20                  |                      |
|        | VAUXN[4]             | LVCMOS18        | IOB_X0Y71            | H18                  |                      |
|        | VAUXN[5]             | LVCMOS18        | IOB_X0Y65            | H20                  |                      |
|        | VAUXN[6]             | LVCMOS18        | IOB_X0Y59            | J14                  |                      |
|        | VAUXN[7]             | LVCMOS18        | IOB_X0Y55            | L15                  |                      |
|        | VAUXN[8]             | LVCMOS18        | IOB_X0Y95            | A20                  |                      |
|        | VAUXN[9]             | LVCMOS18        | IOB_X0Y89            | E19                  |                      |
|        | VAUXP[0]             | LVCMOS18        | IOB_X0Y98            | C20                  |                      |
|        | VAUXP[10]            | LVCMOS18        | IOB_X0Y84            | M17                  |                      |
|        | VAUXP[11]            | LVCMOS18        | IOB_X0Y80            | K19                  |                      |
|        | VAUXP[12]            | LVCMOS18        | IOB_X0Y70            | F19                  |                      |
|        | VAUXP[13]            | LVCMOS18        | IOB_X0Y64            | G19                  |                      |
|        | VAUXP[14]            | LVCMOS18        | IOB_X0Y58            | N15                  |                      |
|        | VAUXP[15]            | LVCMOS18        | IOB_X0Y52            | K16                  |                      |
|        | VAUXP[1]             | LVCMOS18        | IOB_X0Y94            | E17                  |                      |
|        | VAUXP[2]             | LVCMOS18        | IOB_X0Y86            | M19                  |                      |
|        | VAUXP[3]             | LVCMOS18        | IOB_X0Y82            | L19                  |                      |
|        | VAUXP[4]             | LVCMOS18        | IOB_X0Y72            | J18                  |                      |
|        | VAUXP[5]             | LVCMOS18        | IOB_X0Y66            | J20                  |                      |
|        | VAUXP[6]             | LVCMOS18        | IOB_X0Y60            | K14                  |                      |
|        | VAUXP[7]             | LVCMOS18        | IOB_X0Y56            | L14                  |                      |
|        | VAUXP[8]             | LVCMOS18        | IOB_X0Y96            | B19                  |                      |
|        | VAUXP[9]             | LVCMOS18        | IOB_X0Y90            | E18                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
Code: 
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Code: 
[Common 17-69] Command failed: Placer could not place all instances

Any help would be appreciated.
 

I can't seem to duplicate your problems. Here is a testcase I ran that doesn't have any issues with the xadc ios and even has to include an IOSTANDARD on the vaux inputs to allow some of the other pins to reside in the same bank.

FYI there isn't any logic in the design besides the XADC instance.

Regards
 

Attachments

  • xadc.zip
    651 KB · Views: 64

Hi,

UG480 is a bit misleading. Your quote of p26 is correct, but see page 15 where it says Vivado requirements are different from ISE, and a pin location and IOSTANDARD must be set for Vivado.
 

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