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[SOLVED] What is the difference in between TIming Arcs and Timing constraints?

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anirbanphys

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What is the difference in between timing arcs and timing constraints which we use in synopsys .lib file and verilog model file?
Is it possible to check timing arcs and constraints in betwenn .lib and .v file by using SDF?
 

A timing arc is a timing path(say between 2 registers) while timing constraints are the timing requirements(between the same registers) which you provide in a constraints file while synthesizing the design

SDF is a file which provides the transition and the wire delays for the chosen design. You should bring in the .lib file or the model file in this discussion.
 

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