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23rd June 2014, 10:00 #1
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Declaring an unconstraind varaible inside a function
In VHDL 2008
Is it possible to declare an unconsrained unsigned variable in a function?
For example:
Code:function some_function ( x : unsigned ; y : unsigned ) return unsigned is variable result : unsigned ;  "result" is defined as an unconstrained unsigned. begin if x > y then result := x ;  "result" gets constrained according to the size of x else result := y ;  "result" gets constrained according to the size of y end if ; return result ; end function some_function ;

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23rd June 2014, 11:11 #2
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Re: Declaring an unconstraind varaible inside a function
I don't see that VHDL 2008 provides a means to "copy" constraints by a signal or variable assignment as assumed in your code. I don't think that the syntax will be accepted by VHDL 2008.
On the other side, there's a well established method to set the range of internal procedure variables by attributes, which is used e.g. throughout IEEE package functions. Why should we use "unconstrained" bit vectors in this place?
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23rd June 2014, 12:17 #3
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Re: Declaring an unconstraind varaible inside a function
What about that:
https://www.edaboard.com/thread318055.html
Any reason why this shouldn't work?

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23rd June 2014, 12:47 #4
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Re: Declaring an unconstraind varaible inside a function
Unconstrained objects other than ports or function parameters are illegal. They make no sense anyway.
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23rd June 2014, 14:56 #5
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Re: Declaring an unconstraind varaible inside a function
No.
There are a couple of solutions: Since the function above is so simple, you could write it without any intermediate variables like this:
Code:function some_function ( x : unsigned ; y : unsigned ) return unsigned is begin if x > y then return x ; else return y ; end if ; end function some_function ;
Code:function sel(Cond: Boolean; If_True: integer; If_False: integer) return integer is begin if Cond then return If_True; else return If_False; end if; end function sel;
Code:function some_function ( x : unsigned ; y : unsigned ) return unsigned is variable result : unsigned(sel(x>y, x'high, y'high) downto sel(x>y, x'low, y'low));
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