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ADC simulation/characterization

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crazyamd

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is there a good simulation testbench for ADC simulation available? thanks!
 

Re: ADC simulation/characterizationi

Nothing at the simulation level. However you can take Teradyne, Shlumberger, Agilent test subroutines and convert them into Verilog-A.
 

You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
 

Vamsi Mocherla said:
You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
Click to expand...

thanks for you guys' input. that's actually what i did. i'm just wondering if anyone has made a complete simu testbench/flow, preferrablly for cadence.
 

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