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    ADC simulation/characterization

    is there a good simulation testbench for ADC simulation available? thanks!

    •   Alt5th February 2005, 07:39

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    Re: ADC simulation/characterizationi

    Nothing at the simulation level. However you can take Teradyne, Shlumberger, Agilent test subroutines and convert them into Verilog-A.



    •   Alt9th February 2005, 21:55

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    Re: ADC simulation/characterization

    You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models



    •   Alt11th February 2005, 16:58

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    Re: ADC simulation/characterization

    Quote Originally Posted by Vamsi Mocherla
    You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
    thanks for you guys' input. that's actually what i did. i'm just wondering if anyone has made a complete simu testbench/flow, preferrablly for cadence.



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