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VHDL 2008 synthesis and simulation support

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shaiko

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Hello,

Do the major FPGA synthesis tools (ISE/Vivado, Quartus, Sinplify...) fully support VHDL 2008 ?
What about modelsim? Does is it work flawlessly with VHDL 2008?
 

ISE: Not at all
Vivado: nothing yet, but support promised "soon"
Quartus: a few select bits from about Q10 or 11 (matching case statement, if/elsif/else generate, multidimensional unconstrained arrays)
Synplify: full support Afaik
Modelsim: full support from V10 (limited support from 6.6, previous versions have the '93 compatible libraries included)
 
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So...defining an unconstrained 2d array in a package and using entity generics to later constrain it should work with the latest version of Quartus ?
 

In VHDL 93, when I want to define an entity port as an array - I do it in a package like this:

Code: 
type input_port_array is array ( 0 to 255 ) of std_logic_vector ( 31 downto 0 ) ;

My question, can I leave it unconstained in VHDL 2008 - like this:

Code: 
type input_port_array is array ( natural range <> ) of std_logic_vector <> ;

?
 

I checked it, this does work with Modelsim :
Code: 
type input_port_array is array ( natural range <> ) of std_logic_vector ;
But for some reason, this doesn't:
Code: 
type input_port_array is array ( [COLOR="#FF0000"]unsigned[/COLOR] range <> ) of std_logic_vector ;
Why can't I use an unsigned vector instead of an integer?
 

because unsigned is an array type, not an enumerated or integer type.
 
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The concept of unconstrained arrays in VHDL 2008 applies only to those defined inside a package - right?
It won't work on one that's defined in an entity...correct?

I.E: if an unconstrained array type is defined in the declarations section of an entity, it's boundaries must be set when a when it's declared.
 

I dont quite understand the question..

you have been able to have unconstrained port declarations on entities since VHDL '93:

Code: 
entity some_entity is
port (
  a : std_logic_vector --look, no length declared!
  b : unsigned
  c : signed
)

And the length, direction and bouds are determined when you instantiate the entity from the signal connected to it:

Code: 
signal x : std_logic_vector(7 downto 0);
signal y : unsigned(65 downto 43);
signal z : signed(9999999 to 10000000);

inst1 : entity work.some_entity
port map (
  a => x,
  b => y,
  c => z
);

What you are refering to is declaring array or record types containing an unconstrained member:

Code: 
type my_array is array(natural length <>) of std_logic_vector;  --illegal in '93

type my_record is
   a : std_logic_vector;   --again, illegal in '93
end record my_record;

I dont quite understand what you are getting at.. (btw, the above is all supported in Quartus).
 
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Thanks for the elaborate response.
I thought that when you define an unconstrained SLV/unsigned/signed port in VHDL 93 - the tool immediately considers it to be 32 bits long...
 

Nope. You are thinking of an integer. And slv/unsigned/sign or any array are not allowed to be unconstrained when they are instantiated
 
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And slv/unsigned/sign or any array are not allowed to be unconstrained when they are instantiated
Click to expand...
suppose you use an unconstrained array (defined in a package) as an input port to an entity.
If this "array input port" resides in a lower hierarchy there's no problem - it gets constrained according to the element assigned to it.
But what if this "array input port" resides in the top hierarchy? Compilation error?
 

shaiko said:
suppose you use an unconstrained array (defined in a package) as an input port to an entity.
If this "array input port" resides in a lower hierarchy there's no problem - it gets constrained according to the element assigned to it.
But what if this "array input port" resides in the top hierarchy? Compilation error?
Click to expand...
Hierarchy does not matter. Whenever you compile anything, before you can use something it must have been defined previously. If the 'array input port' is a custom thing defined in your own package then you must first 'use work.my-package.all' first. The ordering of files is generally called 'compilation order' whereas 'hierarchy' refers to levels in a design.

Kevin Jennings
 
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    shaiko

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Hello Kevin,

I don't think you understood my question.
I was asking about the using unconstrained arrays...from what I know an unconstrained array in VHDL 2008 "gets" its boundaries during assignment from the object that's being assigned to it.

My question: what if this unconstrained array is an entity input port that resides in the topmost hierarchy?
 

My question: what if this unconstrained array is an entity input port that resides in the topmost hierarchy?
Click to expand...
Counterquestion. What do you think how it should be used? In which situation would you want an unconstrained array port in the top entity?

I'm not aware of a VHDL means to set the actual array bounds in this situation. I assume, there is no reasonable use for an unconstraint external port .
 
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I'm not aware of a VHDL means to set the actual array bounds in this situation. I assume, there is no reasonable use for an unconstraint external port.
Click to expand...
Surely there's non. I'm just asking to know "what if".
 

It would make no sense, as at the top level you always need to assign individual bits to specific pins on an FPGA or ASIC. So you always know the size of the array at that point. So you would get a compilation error if it was left unbound.
 
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shaiko said:
My question: what if this unconstrained array is an entity input port that resides in the topmost hierarchy?
Click to expand...

Then it will compile just fine (analyze), because there is nothing illegal. It will fail during elaboration (I.e. synthesis or the attempt to start a simulation) because the vector bounds have not been defined. In order to complete elaboration there can be nothing structurally left undefined.

Kevin Jennings
 
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Thanks Kevin - this helps a lot.
 

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