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  1. #1
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    How can I solve DRC density errors of my chip?

    Hi,

    I've just designed my chip, but I don't know, how can I solve the DRC density errors such as oxide.DN, Poly.DN, M1 ... M6.DN.

    I think, I have to fill the free places of chip with Metall 1-6, Oxide and Poly. Is it right? Should I connect them to power or ground?

    Thanks for any reply.

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  2. #2
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    Re: How can I solve DRC density errors of my chip?

    If the foundry demands a minimum density then they probably
    have provided in the PDK, their preferred density fill cell. This
    would have dense features on all layers. The cells can be left
    to float, or be tied to something benign (like substrate, where
    it will sit anyway, and substrate-potential metal if you feel the
    need).

    I have preferred however to make my own plate capacitor
    structures which use as many layers as possible, put over
    MOScaps (ditto) and using them for on chip decoupling - at
    least the area is not wasted. The yield and reliability guys
    always whine about gate area, but you're forced to have
    that area by the rules, so shaddap.


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