diff-pair input referred offset and tail current

Would someone please explain why lowering tail current of a diff pair would improve its mismatch (page 468 Razavi) ?

In the same paragraph of the book, it goes on to say that to improve mismatch/noise of a diff-pair, one needs to increase gm. So it makes sense that increasing the W/L ratio of the diff-pair would improve its offset.

However, reducing tail current of a diff-pair would DECREASE its gm, does it not ? Seems contradictory to me.

Thanks!

Gm has a peak and this is usually a little bit below VT. Which
direction you'd go, depends on where you started.

Increasing gm helps kill the backend offset contribution,
whether it improves matching significantly in the diff
pair itself I don't think is the issue. I rarely if ever see
mismatch data besides VT-match, and there only for
a single or very limited number of current densities.
So I wouldn't be very trusting of how well modeled an
operating point dependent mismatch statistics bundle
might be.

Hi dick_freebird,

Thanks for your response. I think I understand what you are saying.

However, my question was much simpler and just in a general sense. Given the mismatch (delta Vt, delta beta), the book says to improve the offset (noise) of the input diff-pair, increase the gm. It also says decreasing the tail current of the diff-pair also reduces the offset (because Vgs-Vt is reduced). But smaller tail current means smaller diff-pair gm. So what is the deal ?

Thanks,
db

dick_freebird said:

Gm has a peak and this is usually a little bit below VT. Which
direction you'd go, depends on where you started.

Increasing gm helps kill the backend offset contribution,
whether it improves matching significantly in the diff
pair itself I don't think is the issue. I rarely if ever see
mismatch data besides VT-match, and there only for
a single or very limited number of current densities.
So I wouldn't be very trusting of how well modeled an
operating point dependent mismatch statistics bundle
might be.

Click to expand...

dbmd said:

However, my question was much simpler and just in a general sense. Given the mismatch (delta Vt, delta beta), the book says to improve the offset (noise) of the input diff-pair, increase the gm.

Click to expand...

.....the book says....

Where? At which page?

Razavi, Design of Analog CMOS Integrated Circuits - Chapter 13, under DC Offsets, page 468, and it's regarding eq (13.69). Also, below is my original post. Thanks.


Would someone please explain why lowering tail current of a diff pair would improve its mismatch (page 468 Razavi) ?

In the same paragraph of the book, it goes on to say that to improve mismatch/noise of a diff-pair, one needs to increase gm. So it makes sense that increasing the W/L ratio of the diff-pair would improve its offset.

However, reducing tail current of a diff-pair would DECREASE its gm, does it not ? Seems contradictory to me.

Thanks!

LvW said:

.....the book says....

Where? At which page?

Click to expand...

dbmd said:

Would someone please explain why lowering tail current of a diff pair would improve its mismatch (page 468 Razavi) ?

Click to expand...

The text says that (VGS-VTH) should be lowered, which means: Smaller VGS (VTH is fixed) and, thus, smaller current ID.

dbmd said:

In the same paragraph of the book, it goes on to say that to improve mismatch/noise of a diff-pair, one needs to increase gm. So it makes sense that increasing the W/L ratio of the diff-pair would improve its offset.

Click to expand...

I see, that is below Eq. (13.77), right? And it is mentioned that this is a "trend opposite of that in Eq. (13.69)". This part concerns "current mismatches" (Eq(13.69) concerns offset voltages).

I think, in electronics it is quite normal that it is not easy to find something like "optimum performance". In most cases (if not in all) improvement of one particular performance parameter results in a degredation of another paramter. Thus, always a trade-off has to be found.
And exactly this is the task of a good engineer: To find a good trade-off between several conflicting parameters.
(Example: Transistor gain stage. Increased DC current Ic gives larger gm and allows more gain. Consequence: Reduced input resistance).