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system verilog verification to vhdl design code

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mohamed mahmoud

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i,am very new to "SystemVerilog for Verification"
question :
i have written code with vhdl , is it possible to write testbenchs with system verilog to verify my ''vhdl'' code ??

if it yes : hopefully anyone to provide tutorials about system verilog (i don,t need slides that has small information and also don,t need big reference)
 

The short answer is yes you can.

Though you will require a mixed language simulator that has full SV support, like Questa, Riviera, Incisive, etc. Most of those tools are $20K-$30K tools.

I've only run across one free SV tutorial for someone without a company email address. It was posted by the creator of the tutorial. I haven't looked at it beyond the front page, as I've been more interested in learning UVM through Mentor's site https://verificationacademy.com/, which requires that you register with a company email address.

Regards
 
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