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Vivado synthesis fail. conditional expression could not be resolved to a constant.

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BartlebyScrivener

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When I try to synthesize with Vivado It seems to not like the way I do my generate loops ... I get the following error

Code: 
[Synth 8-196] conditional expression could not be resolved to a constant [filename]

But the code works in simulation, and synthesis with quartus. Googling the error doesn't bring up anything really.

What could this be? This is my first attempt with Vivado so it may be silly, but the way I write my generate loops is as follows.


Code Verilog - [expand]
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genvar i;
  generate
    for (i=0; i<M; i++) begin : VIRTUAL_CHANNELS
    // code here
    end
  endgenerate



Thanks/
 

Ok, for example

Code Verilog - [expand]
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(parameter integer INPUT_QUEUE_DEPTH = 4,
  parameter integer N = 5,
  parameter integer M = 5)
 
    genvar i;
 
    generate
      for(i=0; i<N; i++) begin : GENERATE_VOQ
        LIB_VOQ #(.M(M), .DEPTH(INPUT_QUEUE_DEPTH))
          gen_LIB_VOQ (.clk,
                       .ce,
                       .reset_n,
                       .i_data(l_i_data[i]),         // Single input data from upstream router
                       .i_data_val(l_vc_req[i]),     // Valid from routecalc corresponds to required VC
                       .o_en(l_o_en[i]),
                       .o_data(l_data[i]),           // Single output data to switch
                       .o_data_val(l_output_req[i]), // Packed request word to SwitchControl
                       .i_en(l_en[i]));              // Packed grant word from SwitchControl
      end
    endgenerate


gives the error

[Synth 8-196] conditional expression could not be resolved to a constant ["filename":158]

where line 158 is the line

Code Verilog - [expand]
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for(i=0; i<N; i++) begin : GENERATE_VOQ


- - - Updated - - -

I just added a space after for and it started to synthesize.
 

Perhaps the syntax of the for loop should mimic verilog's syntax contraints for incrementing:

for example:

Code: 
//synthesizes
count_reg <= count_reg + 1;

//fails
count_reg <= count_reg++;

//for loop syntax
for(i=0; i<N; i=i+1) begin : GENERATE_VOQ
 

Code Verilog - [expand]
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//synthesizes
count_reg <= count_reg + 1;   // ads-ee: This is legal Verilog syntax
 
//fails
count_reg <= count_reg++;  // ads-ee: This isn't leagal Verilog or System Verilog syntax, so why are you giving a "C" sytnax example?
 
//for loop syntax
for(i=0; i<N; i=i+1) begin : GENERATE_VOQ   // ads-ee: this is leagal Verilog syntax
 
//for loop syntax
for(i=0; i<N; i++) begin : GENERATE_VOQ   // ads-ee: this is leagal System Verilog syntax, which Vivado does support for synthesis,
                                          // but according to the OP the parser has a problem with "for(" (no space) and doesn't with "for (" (with space).
 

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